Merge #1037
1037: Add uart async task example r=miathedev a=miathedev Dear Embassy Team, here i propose an additional async uart pass-through example for the STM32WL. Because im quite new to Rust, is there something like **interfaces**? The code: ``` mut usart1: Uart< 'static, embassy_stm32::peripherals::USART1, embassy_stm32::peripherals::DMA1_CH3, embassy_stm32::peripherals::DMA1_CH4, >, mut usart2: Uart< 'static, embassy_stm32::peripherals::LPUART1, embassy_stm32::peripherals::DMA1_CH5, embassy_stm32::peripherals::DMA1_CH6, >, ``` is quite ugly in my opinion. I would like to allow any Type of DMA and USART/UART as argument. Is this possible somehow? Im open to any feedback. With love, Mia Co-authored-by: miathedev <mia@metzler.systems>
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examples/stm32wl/src/bin/uart_async.rs
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examples/stm32wl/src/bin/uart_async.rs
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#![no_std]
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#![no_main]
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#![feature(type_alias_impl_trait)]
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use defmt::*;
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use embassy_executor::Spawner;
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use embassy_stm32::interrupt;
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use embassy_stm32::usart::{Config, Uart};
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use {defmt_rtt as _, panic_probe as _};
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/*
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Pass Incoming data from LPUART1 to USART1
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Example is written for the LoRa-E5 mini v1.0,
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but can be surely changed for your needs.
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*/
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#[embassy_executor::main]
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async fn main(_spawner: Spawner) {
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let mut config = embassy_stm32::Config::default();
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config.rcc.mux = embassy_stm32::rcc::ClockSrc::HSE32;
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let p = embassy_stm32::init(config);
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defmt::info!("Starting system");
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let mut config1 = Config::default();
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config1.baudrate = 9600;
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let mut config2 = Config::default();
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config2.baudrate = 9600;
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//RX/TX connected to USB/UART Bridge on LoRa-E5 mini v1.0
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let irq = interrupt::take!(USART1);
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let mut usart1 = Uart::new(p.USART1, p.PB7, p.PB6, irq, p.DMA1_CH3, p.DMA1_CH4, config1);
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//RX1/TX1 (LPUART) on LoRa-E5 mini v1.0
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let irq = interrupt::take!(LPUART1);
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let mut usart2 = Uart::new(p.LPUART1, p.PC0, p.PC1, irq, p.DMA1_CH5, p.DMA1_CH6, config2);
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unwrap!(usart1.write(b"Hello Embassy World!\r\n").await);
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unwrap!(usart2.write(b"Hello Embassy World!\r\n").await);
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let mut buf = [0u8; 300];
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loop {
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let result = usart2.read_until_idle(&mut buf).await;
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match result {
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Ok(size) => {
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match usart1.write(&buf[0..size]).await {
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Ok(()) => {
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//Write suc.
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}
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Err(..) => {
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//Wasnt able to write
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}
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}
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}
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Err(_err) => {
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//Ignore eg. framing errors
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}
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}
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}
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}
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