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Fix build with all nrf chip models

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This commit is contained in:
Dario Nieuwenhuis 2020-10-31 23:03:09 +01:00
parent 2684bf605a
commit 0643095695
7 changed files with 50 additions and 19 deletions
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17
embassy-nrf/Cargo.toml
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@ -12,11 +12,11 @@ defmt-info = []
defmt-warn = []
defmt-error = []
52810 = ["nrf52810-pac"]
52811 = ["nrf52811-pac"]
52832 = ["nrf52832-pac"]
52833 = ["nrf52833-pac"]
52840 = ["nrf52840-pac"]
52810 = ["nrf52810-pac", "nrf52810-hal"]
52811 = ["nrf52811-pac"] #, "nrf52811-hal"]
52832 = ["nrf52832-pac", "nrf52832-hal"]
52833 = ["nrf52833-pac", "nrf52833-hal"]
52840 = ["nrf52840-pac", "nrf52840-hal"]
[dependencies]
@ -24,7 +24,6 @@ embassy = { version = "0.1.0", path = "../embassy" }
cortex-m-rt = "0.6.12"
cortex-m = { version = "0.6.3" }
embedded-hal = { version = "0.2.4" }
nrf52840-hal = { version = "0.11.0" }
bare-metal = { version = "0.2.0", features = ["const-fn"] }
defmt = "0.1.0"
@ -33,3 +32,9 @@ nrf52811-pac = { version = "0.9.0", optional = true }
nrf52832-pac = { version = "0.9.0", optional = true }
nrf52833-pac = { version = "0.9.0", optional = true }
nrf52840-pac = { version = "0.9.0", optional = true }
nrf52810-hal = { version = "0.11.0", optional = true }
#nrf52811-hal = { version = "0.11.0", optional = true } # doesn't exist yet
nrf52832-hal = { version = "0.11.0", optional = true }
nrf52833-hal = { version = "0.11.0", optional = true }
nrf52840-hal = { version = "0.11.0", optional = true }

4
embassy-nrf/src/gpiote.rs
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@ -2,8 +2,8 @@ use core::cell::Cell;
use core::ptr;
use defmt::trace;
use embassy::util::Signal;
use nrf52840_hal::gpio::{Input, Level, Output, Pin, Port};
use crate::hal::gpio::{Input, Level, Output, Pin, Port};
use crate::interrupt;
use crate::pac::generic::Reg;
use crate::pac::gpiote::_TASKS_OUT;
@ -100,6 +100,7 @@ impl Gpiote {
EventPolarity::None => w.mode().event().polarity().none(),
EventPolarity::Toggle => w.mode().event().polarity().toggle(),
};
#[cfg(any(feature = "52833", feature = "52840"))]
w.port().bit(match pin.port() {
Port::Port0 => false,
Port::Port1 => true,
@ -140,6 +141,7 @@ impl Gpiote {
TaskOutPolarity::Clear => w.polarity().hi_to_lo(),
TaskOutPolarity::Toggle => w.polarity().toggle(),
};
#[cfg(any(feature = "52833", feature = "52840"))]
w.port().bit(match pin.port() {
Port::Port0 => false,
Port::Port1 => true,

2
embassy-nrf/src/interrupt.rs
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@ -3,7 +3,7 @@
//! This module implements an API for managing interrupts compatible with
//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
use core::sync::atomic::{compiler_fence, Ordering};
use crate::pac::{NVIC, NVIC_PRIO_BITS};

12
embassy-nrf/src/lib.rs
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@ -37,8 +37,20 @@ pub use nrf52833_pac as pac;
#[cfg(feature = "52840")]
pub use nrf52840_pac as pac;
#[cfg(feature = "52810")]
pub use nrf52810_hal as hal;
#[cfg(feature = "52811")]
pub use nrf52811_hal as hal;
#[cfg(feature = "52832")]
pub use nrf52832_hal as hal;
#[cfg(feature = "52833")]
pub use nrf52833_hal as hal;
#[cfg(feature = "52840")]
pub use nrf52840_hal as hal;
pub mod gpiote;
pub mod interrupt;
#[cfg(feature = "52840")]
pub mod qspi;
pub mod rtc;
pub mod uarte;

7
embassy-nrf/src/qspi.rs
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@ -1,6 +1,7 @@
use crate::pac::{Interrupt, QSPI};
use core::future::Future;
use nrf52840_hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
use crate::hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
use crate::pac::{Interrupt, QSPI};
pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
pub use crate::pac::qspi::ifconfig0::PPSIZE_A as WritePageSize;
@ -314,7 +315,7 @@ static SIGNAL: Signal<()> = Signal::new();
#[interrupt]
unsafe fn QSPI() {
let p = unsafe { crate::pac::Peripherals::steal().QSPI };
let p = crate::pac::Peripherals::steal().QSPI;
if p.events_ready.read().events_ready().bit_is_set() {
p.events_ready.reset();
SIGNAL.signal(());

4
embassy-nrf/src/rtc.rs
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@ -96,8 +96,8 @@ impl<T: Instance> RTC<T> {
w
});
self.rtc.tasks_clear.write(|w| w.tasks_clear().set_bit());
self.rtc.tasks_start.write(|w| w.tasks_start().set_bit());
self.rtc.tasks_clear.write(|w| unsafe { w.bits(1) });
self.rtc.tasks_start.write(|w| unsafe { w.bits(1) });
// Wait for clear
while self.rtc.counter.read().bits() != 0 {}

23
embassy-nrf/src/uarte.rs
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@ -13,11 +13,14 @@ use core::ptr;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use embedded_hal::digital::v2::OutputPin;
use crate::hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
use crate::interrupt;
use crate::interrupt::CriticalSection;
use crate::pac::{uarte0, Interrupt, UARTE0, UARTE1};
use embedded_hal::digital::v2::OutputPin;
use nrf52840_hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
use crate::pac::UARTE1;
use crate::pac::{uarte0, Interrupt, UARTE0};
// Re-export SVD variants to allow user to directly set values
pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
@ -152,6 +155,7 @@ pub struct UarteState<T> {
_pin: PhantomPinned,
}
#[cfg(any(feature = "52833", feature = "52840"))]
fn port_bit(port: GpioPort) -> bool {
match port {
GpioPort::Port0 => false,
@ -164,12 +168,14 @@ impl<T: Instance> Uarte<T> {
// Select pins
uarte.psel.rxd.write(|w| {
let w = unsafe { w.pin().bits(pins.rxd.pin()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.rxd.port()));
w.connect().connected()
});
pins.txd.set_high().unwrap();
uarte.psel.txd.write(|w| {
let w = unsafe { w.pin().bits(pins.txd.pin()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pins.txd.port()));
w.connect().connected()
});
@ -178,6 +184,7 @@ impl<T: Instance> Uarte<T> {
uarte.psel.cts.write(|w| {
if let Some(ref pin) = pins.cts {
let w = unsafe { w.pin().bits(pin.pin()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
@ -188,6 +195,7 @@ impl<T: Instance> Uarte<T> {
uarte.psel.rts.write(|w| {
if let Some(ref pin) = pins.rts {
let w = unsafe { w.pin().bits(pin.pin()) };
#[cfg(any(feature = "52833", feature = "52840"))]
let w = w.port().bit(port_bit(pin.port()));
w.connect().connected()
} else {
@ -493,11 +501,11 @@ pub struct Pins {
}
mod private {
use nrf52840_pac::{UARTE0, UARTE1};
pub trait Sealed {}
impl Sealed for UARTE0 {}
impl Sealed for UARTE1 {}
impl Sealed for crate::pac::UARTE0 {}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl Sealed for crate::pac::UARTE1 {}
}
pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sealed {
@ -515,12 +523,14 @@ unsafe fn UARTE0_UART0() {
interrupt::free(|cs| UARTE0::get_state(cs).as_mut().unwrap().on_interrupt());
}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
#[interrupt]
unsafe fn UARTE1() {
interrupt::free(|cs| UARTE1::get_state(cs).as_mut().unwrap().on_interrupt());
}
static mut UARTE0_STATE: *mut UarteState<UARTE0> = ptr::null_mut();
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
static mut UARTE1_STATE: *mut UarteState<UARTE1> = ptr::null_mut();
impl Instance for UARTE0 {
@ -536,6 +546,7 @@ impl Instance for UARTE0 {
}
}
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
impl Instance for UARTE1 {
fn interrupt() -> Interrupt {
Interrupt::UARTE1