Fix build with all nrf chip models
This commit is contained in:
		@@ -12,11 +12,11 @@ defmt-info = []
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defmt-warn = []
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defmt-error = []
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52810 = ["nrf52810-pac"]
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52811 = ["nrf52811-pac"]
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52832 = ["nrf52832-pac"]
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52833 = ["nrf52833-pac"]
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52840 = ["nrf52840-pac"]
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52810 = ["nrf52810-pac", "nrf52810-hal"]
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52811 = ["nrf52811-pac"] #, "nrf52811-hal"]
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52832 = ["nrf52832-pac", "nrf52832-hal"]
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52833 = ["nrf52833-pac", "nrf52833-hal"]
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52840 = ["nrf52840-pac", "nrf52840-hal"]
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[dependencies]
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@@ -24,7 +24,6 @@ embassy = { version = "0.1.0", path = "../embassy" }
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cortex-m-rt = "0.6.12"
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cortex-m        = { version = "0.6.3" }
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embedded-hal    = { version = "0.2.4" }
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nrf52840-hal    = { version = "0.11.0" }
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bare-metal = { version = "0.2.0", features = ["const-fn"] }
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defmt = "0.1.0"
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@@ -33,3 +32,9 @@ nrf52811-pac  = { version = "0.9.0", optional = true }
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nrf52832-pac  = { version = "0.9.0", optional = true }
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nrf52833-pac  = { version = "0.9.0", optional = true }
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nrf52840-pac  = { version = "0.9.0", optional = true }
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nrf52810-hal  = { version = "0.11.0", optional = true }
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#nrf52811-hal  = { version = "0.11.0", optional = true }  # doesn't exist yet
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nrf52832-hal  = { version = "0.11.0", optional = true }
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nrf52833-hal  = { version = "0.11.0", optional = true }
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nrf52840-hal  = { version = "0.11.0", optional = true }
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@@ -2,8 +2,8 @@ use core::cell::Cell;
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use core::ptr;
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use defmt::trace;
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use embassy::util::Signal;
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use nrf52840_hal::gpio::{Input, Level, Output, Pin, Port};
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use crate::hal::gpio::{Input, Level, Output, Pin, Port};
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use crate::interrupt;
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use crate::pac::generic::Reg;
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use crate::pac::gpiote::_TASKS_OUT;
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@@ -100,6 +100,7 @@ impl Gpiote {
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                    EventPolarity::None => w.mode().event().polarity().none(),
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                    EventPolarity::Toggle => w.mode().event().polarity().toggle(),
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                };
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                #[cfg(any(feature = "52833", feature = "52840"))]
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                w.port().bit(match pin.port() {
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                    Port::Port0 => false,
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                    Port::Port1 => true,
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@@ -140,6 +141,7 @@ impl Gpiote {
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                    TaskOutPolarity::Clear => w.polarity().hi_to_lo(),
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                    TaskOutPolarity::Toggle => w.polarity().toggle(),
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                };
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                #[cfg(any(feature = "52833", feature = "52840"))]
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                w.port().bit(match pin.port() {
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                    Port::Port0 => false,
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                    Port::Port1 => true,
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@@ -3,7 +3,7 @@
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//! This module implements an API for managing interrupts compatible with
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//! nrf_softdevice::interrupt. Intended for switching between the two at compile-time.
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use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
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use core::sync::atomic::{compiler_fence, Ordering};
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use crate::pac::{NVIC, NVIC_PRIO_BITS};
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@@ -37,8 +37,20 @@ pub use nrf52833_pac as pac;
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#[cfg(feature = "52840")]
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pub use nrf52840_pac as pac;
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#[cfg(feature = "52810")]
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pub use nrf52810_hal as hal;
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#[cfg(feature = "52811")]
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pub use nrf52811_hal as hal;
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#[cfg(feature = "52832")]
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pub use nrf52832_hal as hal;
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#[cfg(feature = "52833")]
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pub use nrf52833_hal as hal;
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#[cfg(feature = "52840")]
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pub use nrf52840_hal as hal;
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pub mod gpiote;
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pub mod interrupt;
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#[cfg(feature = "52840")]
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pub mod qspi;
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pub mod rtc;
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pub mod uarte;
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@@ -1,6 +1,7 @@
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use crate::pac::{Interrupt, QSPI};
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use core::future::Future;
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use nrf52840_hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
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use crate::hal::gpio::{Output, Pin as GpioPin, Port as GpioPort, PushPull};
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use crate::pac::{Interrupt, QSPI};
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pub use crate::pac::qspi::ifconfig0::ADDRMODE_A as AddressMode;
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pub use crate::pac::qspi::ifconfig0::PPSIZE_A as WritePageSize;
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@@ -314,7 +315,7 @@ static SIGNAL: Signal<()> = Signal::new();
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#[interrupt]
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unsafe fn QSPI() {
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    let p = unsafe { crate::pac::Peripherals::steal().QSPI };
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    let p = crate::pac::Peripherals::steal().QSPI;
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    if p.events_ready.read().events_ready().bit_is_set() {
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        p.events_ready.reset();
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        SIGNAL.signal(());
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@@ -96,8 +96,8 @@ impl<T: Instance> RTC<T> {
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            w
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        });
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        self.rtc.tasks_clear.write(|w| w.tasks_clear().set_bit());
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        self.rtc.tasks_start.write(|w| w.tasks_start().set_bit());
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        self.rtc.tasks_clear.write(|w| unsafe { w.bits(1) });
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        self.rtc.tasks_start.write(|w| unsafe { w.bits(1) });
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        // Wait for clear
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        while self.rtc.counter.read().bits() != 0 {}
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@@ -13,11 +13,14 @@ use core::ptr;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::{Context, Poll};
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use embedded_hal::digital::v2::OutputPin;
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use crate::hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
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use crate::interrupt;
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use crate::interrupt::CriticalSection;
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use crate::pac::{uarte0, Interrupt, UARTE0, UARTE1};
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use embedded_hal::digital::v2::OutputPin;
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use nrf52840_hal::gpio::{Floating, Input, Output, Pin as GpioPin, Port as GpioPort, PushPull};
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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use crate::pac::UARTE1;
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use crate::pac::{uarte0, Interrupt, UARTE0};
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// Re-export SVD variants to allow user to directly set values
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pub use uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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@@ -152,6 +155,7 @@ pub struct UarteState<T> {
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    _pin: PhantomPinned,
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}
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#[cfg(any(feature = "52833", feature = "52840"))]
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fn port_bit(port: GpioPort) -> bool {
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    match port {
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        GpioPort::Port0 => false,
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@@ -164,12 +168,14 @@ impl<T: Instance> Uarte<T> {
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        // Select pins
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        uarte.psel.rxd.write(|w| {
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            let w = unsafe { w.pin().bits(pins.rxd.pin()) };
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            #[cfg(any(feature = "52833", feature = "52840"))]
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            let w = w.port().bit(port_bit(pins.rxd.port()));
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            w.connect().connected()
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        });
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        pins.txd.set_high().unwrap();
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        uarte.psel.txd.write(|w| {
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            let w = unsafe { w.pin().bits(pins.txd.pin()) };
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            #[cfg(any(feature = "52833", feature = "52840"))]
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            let w = w.port().bit(port_bit(pins.txd.port()));
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            w.connect().connected()
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        });
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@@ -178,6 +184,7 @@ impl<T: Instance> Uarte<T> {
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        uarte.psel.cts.write(|w| {
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            if let Some(ref pin) = pins.cts {
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                let w = unsafe { w.pin().bits(pin.pin()) };
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                #[cfg(any(feature = "52833", feature = "52840"))]
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                let w = w.port().bit(port_bit(pin.port()));
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                w.connect().connected()
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            } else {
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@@ -188,6 +195,7 @@ impl<T: Instance> Uarte<T> {
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        uarte.psel.rts.write(|w| {
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            if let Some(ref pin) = pins.rts {
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                let w = unsafe { w.pin().bits(pin.pin()) };
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                #[cfg(any(feature = "52833", feature = "52840"))]
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                let w = w.port().bit(port_bit(pin.port()));
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                w.connect().connected()
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            } else {
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@@ -493,11 +501,11 @@ pub struct Pins {
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}
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mod private {
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    use nrf52840_pac::{UARTE0, UARTE1};
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    pub trait Sealed {}
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    impl Sealed for UARTE0 {}
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    impl Sealed for UARTE1 {}
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    impl Sealed for crate::pac::UARTE0 {}
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    #[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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    impl Sealed for crate::pac::UARTE1 {}
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}
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pub trait Instance: Deref<Target = uarte0::RegisterBlock> + Sized + private::Sealed {
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@@ -515,12 +523,14 @@ unsafe fn UARTE0_UART0() {
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    interrupt::free(|cs| UARTE0::get_state(cs).as_mut().unwrap().on_interrupt());
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}
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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#[interrupt]
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unsafe fn UARTE1() {
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    interrupt::free(|cs| UARTE1::get_state(cs).as_mut().unwrap().on_interrupt());
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}
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static mut UARTE0_STATE: *mut UarteState<UARTE0> = ptr::null_mut();
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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static mut UARTE1_STATE: *mut UarteState<UARTE1> = ptr::null_mut();
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impl Instance for UARTE0 {
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@@ -536,6 +546,7 @@ impl Instance for UARTE0 {
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    }
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}
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#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
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impl Instance for UARTE1 {
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    fn interrupt() -> Interrupt {
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        Interrupt::UARTE1
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