initial work porting eth to f107
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@ -12,7 +12,7 @@ use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
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use crate::gpio::sealed::Pin as __GpioPin;
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use crate::gpio::sealed::Pin as __GpioPin;
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use crate::gpio::{sealed::AFType, AnyPin, Speed};
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use crate::gpio::{sealed::AFType, AnyPin, Speed};
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use crate::pac::{ETH, RCC, SYSCFG};
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use crate::pac::{AFIO, ETH, RCC};
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mod descriptors;
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mod descriptors;
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mod rx_desc;
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mod rx_desc;
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@ -47,8 +47,9 @@ macro_rules! config_pins {
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// NOTE(unsafe) Exclusive access to the registers
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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critical_section::with(|_| {
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$(
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$(
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// TODO double check to ensure speed set *isn't required. This call *seems* to set
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// GPIO to max speed.
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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$pin.set_speed(Speed::VeryHigh);
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)*
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)*
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})
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})
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};
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};
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@ -78,15 +79,17 @@ impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T,
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// Enable the necessary Clocks
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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// NOTE(unsafe) We have exclusive access to the registers
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critical_section::with(|_| {
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_syscfgen(true));
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RCC.apb2enr().modify(|w| w.set_afioen(true));
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RCC.ahb1enr().modify(|w| {
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RCC.ahbenr().modify(|w| {
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w.set_ethen(true);
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w.set_ethmacen(true);
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w.set_ethtxen(true);
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w.set_ethmactxen(true);
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w.set_ethrxen(true);
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w.set_ethmacrxen(true);
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});
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});
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// RMII (Reduced Media Independent Interface)
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// Select RMII (Reduced Media Independent Interface)
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SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
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AFIO.mapr().modify(|w| w.set_mii_rmii_sel(true));
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// TODO set MCO to eth clk
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});
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});
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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