Initial import to v1a, does not compile
This commit is contained in:
David Lenfesty
committed by
Dario Nieuwenhuis
Dario Nieuwenhuis
parent
2f43969dd4
commit
f30e5d2d3f
@@ -1,5 +1,6 @@
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#![macro_use]
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#[cfg_attr(eth_v1a, path = "v1a/mod.rs")]
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#[cfg_attr(eth_v1c, path = "v1c/mod.rs")]
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#[cfg_attr(eth_v2, path = "v2/mod.rs")]
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#[cfg_attr(eth_v1, path = "v1.rs")]
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21
embassy-stm32/src/eth/v1a/descriptors.rs
Normal file
21
embassy-stm32/src/eth/v1a/descriptors.rs
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@@ -0,0 +1,21 @@
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use crate::eth::_version::rx_desc::RDesRing;
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use crate::eth::_version::tx_desc::TDesRing;
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pub struct DescriptorRing<const T: usize, const R: usize> {
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pub(crate) tx: TDesRing<T>,
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pub(crate) rx: RDesRing<R>,
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}
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impl<const T: usize, const R: usize> DescriptorRing<T, R> {
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pub const fn new() -> Self {
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Self {
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tx: TDesRing::new(),
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rx: RDesRing::new(),
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}
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}
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pub fn init(&mut self) {
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self.tx.init();
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self.rx.init();
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}
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}
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359
embassy-stm32/src/eth/v1a/mod.rs
Normal file
359
embassy-stm32/src/eth/v1a/mod.rs
Normal file
@@ -0,0 +1,359 @@
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// The v1c ethernet driver was ported to embassy from the awesome stm32-eth project (https://github.com/stm32-rs/stm32-eth).
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use core::marker::PhantomData;
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use core::sync::atomic::{fence, Ordering};
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use core::task::Waker;
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use embassy::util::Unborrow;
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use embassy::waitqueue::AtomicWaker;
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use embassy_hal_common::peripheral::{PeripheralMutex, PeripheralState, StateStorage};
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use embassy_hal_common::unborrow;
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use embassy_net::{Device, DeviceCapabilities, LinkState, PacketBuf, MTU};
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use crate::gpio::sealed::Pin as __GpioPin;
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use crate::gpio::{sealed::AFType, AnyPin, Speed};
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use crate::pac::{ETH, RCC, SYSCFG};
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mod descriptors;
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mod rx_desc;
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mod tx_desc;
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use super::*;
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use descriptors::DescriptorRing;
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use stm32_metapac::eth::vals::{
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Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf,
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};
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pub struct State<'d, T: Instance, const TX: usize, const RX: usize>(
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StateStorage<Inner<'d, T, TX, RX>>,
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);
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impl<'d, T: Instance, const TX: usize, const RX: usize> State<'d, T, TX, RX> {
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pub fn new() -> Self {
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Self(StateStorage::new())
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}
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}
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pub struct Ethernet<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> {
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state: PeripheralMutex<'d, Inner<'d, T, TX, RX>>,
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pins: [AnyPin; 9],
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_phy: P,
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clock_range: Cr,
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phy_addr: u8,
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mac_addr: [u8; 6],
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}
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macro_rules! config_pins {
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($($pin:ident),*) => {
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// NOTE(unsafe) Exclusive access to the registers
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critical_section::with(|_| {
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$(
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$pin.set_as_af($pin.af_num(), AFType::OutputPushPull);
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$pin.set_speed(Speed::VeryHigh);
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)*
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})
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};
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, T, P, TX, RX> {
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/// safety: the returned instance is not leak-safe
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pub unsafe fn new(
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state: &'d mut State<'d, T, TX, RX>,
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peri: impl Unborrow<Target = T> + 'd,
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interrupt: impl Unborrow<Target = crate::interrupt::ETH> + 'd,
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ref_clk: impl Unborrow<Target = impl RefClkPin<T>> + 'd,
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mdio: impl Unborrow<Target = impl MDIOPin<T>> + 'd,
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mdc: impl Unborrow<Target = impl MDCPin<T>> + 'd,
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crs: impl Unborrow<Target = impl CRSPin<T>> + 'd,
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rx_d0: impl Unborrow<Target = impl RXD0Pin<T>> + 'd,
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rx_d1: impl Unborrow<Target = impl RXD1Pin<T>> + 'd,
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tx_d0: impl Unborrow<Target = impl TXD0Pin<T>> + 'd,
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tx_d1: impl Unborrow<Target = impl TXD1Pin<T>> + 'd,
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tx_en: impl Unborrow<Target = impl TXEnPin<T>> + 'd,
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phy: P,
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mac_addr: [u8; 6],
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phy_addr: u8,
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) -> Self {
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unborrow!(interrupt, ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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// Enable the necessary Clocks
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// NOTE(unsafe) We have exclusive access to the registers
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critical_section::with(|_| {
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RCC.apb2enr().modify(|w| w.set_syscfgen(true));
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RCC.ahb1enr().modify(|w| {
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w.set_ethen(true);
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w.set_ethtxen(true);
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w.set_ethrxen(true);
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});
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// RMII (Reduced Media Independent Interface)
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SYSCFG.pmc().modify(|w| w.set_mii_rmii_sel(true));
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});
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config_pins!(ref_clk, mdio, mdc, crs, rx_d0, rx_d1, tx_d0, tx_d1, tx_en);
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// NOTE(unsafe) We are ourselves not leak-safe.
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let state = PeripheralMutex::new_unchecked(interrupt, &mut state.0, || Inner::new(peri));
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// NOTE(unsafe) We have exclusive access to the registers
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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// Reset and wait
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dma.dmabmr().modify(|w| w.set_sr(true));
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while dma.dmabmr().read().sr() {}
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mac.maccr().modify(|w| {
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w.set_ifg(Ifg::IFG96); // inter frame gap 96 bit times
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w.set_apcs(Apcs::STRIP); // automatic padding and crc stripping
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w.set_fes(Fes::FES100); // fast ethernet speed
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w.set_dm(Dm::FULLDUPLEX); // full duplex
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// TODO: Carrier sense ? ECRSFD
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});
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// Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
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// so the LR write must happen after the HR write.
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mac.maca0hr()
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.modify(|w| w.set_maca0h(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
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mac.maca0lr().write(|w| {
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w.set_maca0l(
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u32::from(mac_addr[0])
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| (u32::from(mac_addr[1]) << 8)
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| (u32::from(mac_addr[2]) << 16)
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| (u32::from(mac_addr[3]) << 24),
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)
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});
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// pause time
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mac.macfcr().modify(|w| w.set_pt(0x100));
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// Transfer and Forward, Receive and Forward
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dma.dmaomr().modify(|w| {
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w.set_tsf(Tsf::STOREFORWARD);
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w.set_rsf(Rsf::STOREFORWARD);
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});
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dma.dmabmr().modify(|w| {
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w.set_pbl(Pbl::PBL32) // programmable burst length - 32 ?
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});
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// TODO MTU size setting not found for v1 ethernet, check if correct
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// NOTE(unsafe) We got the peripheral singleton, which means that `rcc::init` was called
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let hclk = crate::rcc::get_freqs().ahb1;
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let hclk_mhz = hclk.0 / 1_000_000;
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// Set the MDC clock frequency in the range 1MHz - 2.5MHz
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let clock_range = match hclk_mhz {
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0..=24 => panic!("Invalid HCLK frequency - should be at least 25 MHz."),
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25..=34 => Cr::CR_20_35, // Divide by 16
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35..=59 => Cr::CR_35_60, // Divide by 26
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60..=99 => Cr::CR_60_100, // Divide by 42
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100..=149 => Cr::CR_100_150, // Divide by 62
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150..=216 => Cr::CR_150_168, // Divide by 102
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_ => {
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panic!("HCLK results in MDC clock > 2.5MHz even for the highest CSR clock divider")
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}
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};
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let pins = [
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ref_clk.degrade(),
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mdio.degrade(),
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mdc.degrade(),
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crs.degrade(),
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rx_d0.degrade(),
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rx_d1.degrade(),
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tx_d0.degrade(),
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tx_d1.degrade(),
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tx_en.degrade(),
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];
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let mut this = Self {
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state,
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pins,
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_phy: phy,
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clock_range,
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phy_addr,
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mac_addr,
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};
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this.state.with(|s| {
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s.desc_ring.init();
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fence(Ordering::SeqCst);
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let mac = ETH.ethernet_mac();
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let dma = ETH.ethernet_dma();
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mac.maccr().modify(|w| {
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w.set_re(true);
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w.set_te(true);
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});
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dma.dmaomr().modify(|w| {
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w.set_ftf(Ftf::FLUSH); // flush transmit fifo (queue)
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w.set_st(St::STARTED); // start transmitting channel
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w.set_sr(DmaomrSr::STARTED); // start receiving channel
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});
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// Enable interrupts
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dma.dmaier().modify(|w| {
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w.set_nise(true);
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w.set_rie(true);
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w.set_tie(true);
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});
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});
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P::phy_reset(&mut this);
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P::phy_init(&mut this);
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this
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}
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}
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unsafe impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> StationManagement
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for Ethernet<'d, T, P, TX, RX>
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{
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fn smi_read(&mut self, reg: u8) -> u16 {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmiiar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::READ); // read operation
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY); // indicate that operation is in progress
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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mac.macmiidr().read().md()
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}
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}
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fn smi_write(&mut self, reg: u8, val: u16) {
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// NOTE(unsafe) These registers aren't used in the interrupt and we have `&mut self`
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unsafe {
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let mac = ETH.ethernet_mac();
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mac.macmiidr().write(|w| w.set_md(val));
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mac.macmiiar().modify(|w| {
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w.set_pa(self.phy_addr);
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w.set_mr(reg);
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w.set_mw(Mw::WRITE); // write
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w.set_cr(self.clock_range);
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w.set_mb(MbProgress::BUSY);
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});
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while mac.macmiiar().read().mb() == MbProgress::BUSY {}
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}
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}
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Device
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for Ethernet<'d, T, P, TX, RX>
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{
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fn is_transmit_ready(&mut self) -> bool {
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self.state.with(|s| s.desc_ring.tx.available())
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}
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fn transmit(&mut self, pkt: PacketBuf) {
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self.state.with(|s| unwrap!(s.desc_ring.tx.transmit(pkt)));
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}
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fn receive(&mut self) -> Option<PacketBuf> {
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self.state.with(|s| s.desc_ring.rx.pop_packet())
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}
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fn register_waker(&mut self, waker: &Waker) {
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WAKER.register(waker);
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}
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fn capabilities(&mut self) -> DeviceCapabilities {
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let mut caps = DeviceCapabilities::default();
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caps.max_transmission_unit = MTU;
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caps.max_burst_size = Some(TX.min(RX));
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caps
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}
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fn link_state(&mut self) -> LinkState {
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if P::poll_link(self) {
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LinkState::Up
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} else {
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LinkState::Down
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}
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}
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fn ethernet_address(&mut self) -> [u8; 6] {
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self.mac_addr
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}
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}
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impl<'d, T: Instance, P: PHY, const TX: usize, const RX: usize> Drop
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for Ethernet<'d, T, P, TX, RX>
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{
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fn drop(&mut self) {
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// NOTE(unsafe) We have `&mut self` and the interrupt doesn't use this registers
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unsafe {
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let dma = ETH.ethernet_dma();
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let mac = ETH.ethernet_mac();
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// Disable the TX DMA and wait for any previous transmissions to be completed
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dma.dmaomr().modify(|w| w.set_st(St::STOPPED));
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// Disable MAC transmitter and receiver
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mac.maccr().modify(|w| {
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w.set_re(false);
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w.set_te(false);
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});
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dma.dmaomr().modify(|w| w.set_sr(DmaomrSr::STOPPED));
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}
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// NOTE(unsafe) Exclusive access to the regs
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critical_section::with(|_| unsafe {
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for pin in self.pins.iter_mut() {
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pin.set_as_disconnected();
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}
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})
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}
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}
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//----------------------------------------------------------------------
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struct Inner<'d, T: Instance, const TX: usize, const RX: usize> {
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_peri: PhantomData<&'d mut T>,
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desc_ring: DescriptorRing<TX, RX>,
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> Inner<'d, T, TX, RX> {
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pub fn new(_peri: impl Unborrow<Target = T> + 'd) -> Self {
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Self {
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_peri: PhantomData,
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desc_ring: DescriptorRing::new(),
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}
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}
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}
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impl<'d, T: Instance, const TX: usize, const RX: usize> PeripheralState for Inner<'d, T, TX, RX> {
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type Interrupt = crate::interrupt::ETH;
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fn on_interrupt(&mut self) {
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unwrap!(self.desc_ring.tx.on_interrupt());
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self.desc_ring.rx.on_interrupt();
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WAKER.wake();
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// TODO: Check and clear more flags
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unsafe {
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let dma = ETH.ethernet_dma();
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dma.dmasr().modify(|w| {
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w.set_ts(true);
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w.set_rs(true);
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w.set_nis(true);
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});
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// Delay two peripheral's clock
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dma.dmasr().read();
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dma.dmasr().read();
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}
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}
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}
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static WAKER: AtomicWaker = AtomicWaker::new();
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309
embassy-stm32/src/eth/v1a/rx_desc.rs
Normal file
309
embassy-stm32/src/eth/v1a/rx_desc.rs
Normal file
@@ -0,0 +1,309 @@
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use core::sync::atomic::{compiler_fence, fence, Ordering};
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use embassy_net::{Packet, PacketBox, PacketBoxExt, PacketBuf};
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use stm32_metapac::eth::vals::{DmaomrSr, Rpd, Rps};
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use vcell::VolatileCell;
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use crate::pac::ETH;
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mod rx_consts {
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/// Owned by DMA engine
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pub const RXDESC_0_OWN: u32 = 1 << 31;
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/// First descriptor
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pub const RXDESC_0_FS: u32 = 1 << 9;
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/// Last descriptor
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pub const RXDESC_0_LS: u32 = 1 << 8;
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/// Error summary
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pub const RXDESC_0_ES: u32 = 1 << 15;
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/// Frame length
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pub const RXDESC_0_FL_MASK: u32 = 0x3FFF;
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pub const RXDESC_0_FL_SHIFT: usize = 16;
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pub const RXDESC_1_RBS_MASK: u32 = 0x0fff;
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/// Second address chained
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pub const RXDESC_1_RCH: u32 = 1 << 14;
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/// End Of Ring
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pub const RXDESC_1_RER: u32 = 1 << 15;
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}
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use rx_consts::*;
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/// Receive Descriptor representation
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///
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/// * rdes0: OWN and Status
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/// * rdes1: allocated buffer length
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/// * rdes2: data buffer address
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/// * rdes3: next descriptor address
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#[repr(C)]
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struct RDes {
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rdes0: VolatileCell<u32>,
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rdes1: VolatileCell<u32>,
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rdes2: VolatileCell<u32>,
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rdes3: VolatileCell<u32>,
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}
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impl RDes {
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pub const fn new() -> Self {
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Self {
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rdes0: VolatileCell::new(0),
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rdes1: VolatileCell::new(0),
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rdes2: VolatileCell::new(0),
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rdes3: VolatileCell::new(0),
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}
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}
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/// Return true if this RDes is acceptable to us
|
||||
#[inline(always)]
|
||||
pub fn valid(&self) -> bool {
|
||||
// Write-back descriptor is valid if:
|
||||
//
|
||||
// Contains first buffer of packet AND contains last buf of
|
||||
// packet AND no errors
|
||||
(self.rdes0.get() & (RXDESC_0_ES | RXDESC_0_FS | RXDESC_0_LS))
|
||||
== (RXDESC_0_FS | RXDESC_0_LS)
|
||||
}
|
||||
|
||||
/// Return true if this RDes is not currently owned by the DMA
|
||||
#[inline(always)]
|
||||
pub fn available(&self) -> bool {
|
||||
self.rdes0.get() & RXDESC_0_OWN == 0 // Owned by us
|
||||
}
|
||||
|
||||
/// Configures the reception buffer address and length and passed descriptor ownership to the DMA
|
||||
#[inline(always)]
|
||||
pub fn set_ready(&mut self, buf_addr: u32, buf_len: usize) {
|
||||
self.rdes1
|
||||
.set(self.rdes1.get() | (buf_len as u32) & RXDESC_1_RBS_MASK);
|
||||
self.rdes2.set(buf_addr);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
compiler_fence(Ordering::Release);
|
||||
|
||||
self.rdes0.set(self.rdes0.get() | RXDESC_0_OWN);
|
||||
|
||||
// Used to flush the store buffer as fast as possible to make the buffer available for the
|
||||
// DMA.
|
||||
fence(Ordering::SeqCst);
|
||||
}
|
||||
|
||||
// points to next descriptor (RCH)
|
||||
#[inline(always)]
|
||||
fn set_buffer2(&mut self, buffer: *const u8) {
|
||||
self.rdes3.set(buffer as u32);
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn set_end_of_ring(&mut self) {
|
||||
self.rdes1.set(self.rdes1.get() | RXDESC_1_RER);
|
||||
}
|
||||
|
||||
#[inline(always)]
|
||||
fn packet_len(&self) -> usize {
|
||||
((self.rdes0.get() >> RXDESC_0_FL_SHIFT) & RXDESC_0_FL_MASK) as usize
|
||||
}
|
||||
|
||||
pub fn setup(&mut self, next: Option<&Self>) {
|
||||
// Defer this initialization to this function, so we can have `RingEntry` on bss.
|
||||
self.rdes1.set(self.rdes1.get() | RXDESC_1_RCH);
|
||||
|
||||
match next {
|
||||
Some(next) => self.set_buffer2(next as *const _ as *const u8),
|
||||
None => {
|
||||
self.set_buffer2(0 as *const u8);
|
||||
self.set_end_of_ring();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Running state of the `RxRing`
|
||||
#[derive(PartialEq, Eq, Debug)]
|
||||
pub enum RunningState {
|
||||
Unknown,
|
||||
Stopped,
|
||||
Running,
|
||||
}
|
||||
|
||||
impl RunningState {
|
||||
/// whether self equals to `RunningState::Running`
|
||||
pub fn is_running(&self) -> bool {
|
||||
*self == RunningState::Running
|
||||
}
|
||||
}
|
||||
|
||||
/// Rx ring of descriptors and packets
|
||||
///
|
||||
/// This ring has three major locations that work in lock-step. The DMA will never write to the tail
|
||||
/// index, so the `read_index` must never pass the tail index. The `next_tail_index` is always 1
|
||||
/// slot ahead of the real tail index, and it must never pass the `read_index` or it could overwrite
|
||||
/// a packet still to be passed to the application.
|
||||
///
|
||||
/// nt can't pass r (no alloc)
|
||||
/// +---+---+---+---+ Read ok +---+---+---+---+ No Read +---+---+---+---+
|
||||
/// | | | | | ------------> | | | | | ------------> | | | | |
|
||||
/// +---+---+---+---+ Allocation ok +---+---+---+---+ +---+---+---+---+
|
||||
/// ^ ^t ^t ^ ^t ^
|
||||
/// |r |r |r
|
||||
/// |nt |nt |nt
|
||||
///
|
||||
///
|
||||
/// +---+---+---+---+ Read ok +---+---+---+---+ Can't read +---+---+---+---+
|
||||
/// | | | | | ------------> | | | | | ------------> | | | | |
|
||||
/// +---+---+---+---+ Allocation fail +---+---+---+---+ Allocation ok +---+---+---+---+
|
||||
/// ^ ^t ^ ^t ^ ^ ^ ^t
|
||||
/// |r | |r | | |r
|
||||
/// |nt |nt |nt
|
||||
///
|
||||
pub(crate) struct RDesRing<const N: usize> {
|
||||
descriptors: [RDes; N],
|
||||
buffers: [Option<PacketBox>; N],
|
||||
read_index: usize,
|
||||
next_tail_index: usize,
|
||||
}
|
||||
|
||||
impl<const N: usize> RDesRing<N> {
|
||||
pub const fn new() -> Self {
|
||||
const RDES: RDes = RDes::new();
|
||||
const BUFFERS: Option<PacketBox> = None;
|
||||
|
||||
Self {
|
||||
descriptors: [RDES; N],
|
||||
buffers: [BUFFERS; N],
|
||||
read_index: 0,
|
||||
next_tail_index: 0,
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn init(&mut self) {
|
||||
assert!(N > 1);
|
||||
let mut last_index = 0;
|
||||
for (index, buf) in self.buffers.iter_mut().enumerate() {
|
||||
let pkt = match PacketBox::new(Packet::new()) {
|
||||
Some(p) => p,
|
||||
None => {
|
||||
if index == 0 {
|
||||
panic!("Could not allocate at least one buffer for Ethernet receiving");
|
||||
} else {
|
||||
break;
|
||||
}
|
||||
}
|
||||
};
|
||||
self.descriptors[index].set_ready(pkt.as_ptr() as u32, pkt.len());
|
||||
*buf = Some(pkt);
|
||||
last_index = index;
|
||||
}
|
||||
self.next_tail_index = (last_index + 1) % N;
|
||||
|
||||
// not sure if this is supposed to span all of the descriptor or just those that contain buffers
|
||||
{
|
||||
let mut previous: Option<&mut RDes> = None;
|
||||
for entry in self.descriptors.iter_mut() {
|
||||
if let Some(prev) = &mut previous {
|
||||
prev.setup(Some(entry));
|
||||
}
|
||||
previous = Some(entry);
|
||||
}
|
||||
|
||||
if let Some(entry) = &mut previous {
|
||||
entry.setup(None);
|
||||
}
|
||||
}
|
||||
|
||||
// Register txdescriptor start
|
||||
// NOTE (unsafe) Used for atomic writes
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmardlar()
|
||||
.write(|w| w.0 = &self.descriptors as *const _ as u32);
|
||||
};
|
||||
// We already have fences in `set_owned`, which is called in `setup`
|
||||
|
||||
// Start receive
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmaomr()
|
||||
.modify(|w| w.set_sr(DmaomrSr::STARTED))
|
||||
};
|
||||
|
||||
self.demand_poll();
|
||||
}
|
||||
|
||||
fn demand_poll(&self) {
|
||||
unsafe { ETH.ethernet_dma().dmarpdr().write(|w| w.set_rpd(Rpd::POLL)) };
|
||||
}
|
||||
|
||||
pub(crate) fn on_interrupt(&mut self) {
|
||||
// XXX: Do we need to do anything here ? Maybe we should try to advance the tail ptr, but it
|
||||
// would soon hit the read ptr anyway, and we will wake smoltcp's stack on the interrupt
|
||||
// which should try to pop a packet...
|
||||
}
|
||||
|
||||
/// Get current `RunningState`
|
||||
fn running_state(&self) -> RunningState {
|
||||
match unsafe { ETH.ethernet_dma().dmasr().read().rps() } {
|
||||
// Reset or Stop Receive Command issued
|
||||
Rps::STOPPED => RunningState::Stopped,
|
||||
// Fetching receive transfer descriptor
|
||||
Rps::RUNNINGFETCHING => RunningState::Running,
|
||||
// Waiting for receive packet
|
||||
Rps::RUNNINGWAITING => RunningState::Running,
|
||||
// Receive descriptor unavailable
|
||||
Rps::SUSPENDED => RunningState::Stopped,
|
||||
// Closing receive descriptor
|
||||
Rps(0b101) => RunningState::Running,
|
||||
// Transferring the receive packet data from receive buffer to host memory
|
||||
Rps::RUNNINGWRITING => RunningState::Running,
|
||||
_ => RunningState::Unknown,
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) fn pop_packet(&mut self) -> Option<PacketBuf> {
|
||||
if !self.running_state().is_running() {
|
||||
self.demand_poll();
|
||||
}
|
||||
// Not sure if the contents of the write buffer on the M7 can affects reads, so we are using
|
||||
// a DMB here just in case, it also serves as a hint to the compiler that we're syncing the
|
||||
// buffer (I think .-.)
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
let read_available = self.descriptors[self.read_index].available();
|
||||
let tail_index = (self.next_tail_index + N - 1) % N;
|
||||
|
||||
let pkt = if read_available && self.read_index != tail_index {
|
||||
let pkt = self.buffers[self.read_index].take();
|
||||
let len = self.descriptors[self.read_index].packet_len();
|
||||
|
||||
assert!(pkt.is_some());
|
||||
let valid = self.descriptors[self.read_index].valid();
|
||||
|
||||
self.read_index = (self.read_index + 1) % N;
|
||||
if valid {
|
||||
pkt.map(|p| p.slice(0..len))
|
||||
} else {
|
||||
None
|
||||
}
|
||||
} else {
|
||||
None
|
||||
};
|
||||
|
||||
// Try to advance the tail_index
|
||||
if self.next_tail_index != self.read_index {
|
||||
match PacketBox::new(Packet::new()) {
|
||||
Some(b) => {
|
||||
let addr = b.as_ptr() as u32;
|
||||
let buffer_len = b.len();
|
||||
self.buffers[self.next_tail_index].replace(b);
|
||||
self.descriptors[self.next_tail_index].set_ready(addr, buffer_len);
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
self.next_tail_index = (self.next_tail_index + 1) % N;
|
||||
}
|
||||
None => {}
|
||||
}
|
||||
}
|
||||
pkt
|
||||
}
|
||||
}
|
||||
238
embassy-stm32/src/eth/v1a/tx_desc.rs
Normal file
238
embassy-stm32/src/eth/v1a/tx_desc.rs
Normal file
@@ -0,0 +1,238 @@
|
||||
use core::sync::atomic::{compiler_fence, fence, Ordering};
|
||||
|
||||
use embassy_net::PacketBuf;
|
||||
use stm32_metapac::eth::vals::St;
|
||||
use vcell::VolatileCell;
|
||||
|
||||
use crate::pac::ETH;
|
||||
|
||||
#[non_exhaustive]
|
||||
#[derive(Debug, Copy, Clone)]
|
||||
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
|
||||
pub enum Error {
|
||||
NoBufferAvailable,
|
||||
// TODO: Break down this error into several others
|
||||
TransmissionError,
|
||||
}
|
||||
|
||||
/// Transmit and Receive Descriptor fields
|
||||
#[allow(dead_code)]
|
||||
mod tx_consts {
|
||||
pub const TXDESC_0_OWN: u32 = 1 << 31;
|
||||
pub const TXDESC_0_IOC: u32 = 1 << 30;
|
||||
// First segment of frame
|
||||
pub const TXDESC_0_FS: u32 = 1 << 28;
|
||||
// Last segment of frame
|
||||
pub const TXDESC_0_LS: u32 = 1 << 29;
|
||||
// Transmit end of ring
|
||||
pub const TXDESC_0_TER: u32 = 1 << 21;
|
||||
// Second address chained
|
||||
pub const TXDESC_0_TCH: u32 = 1 << 20;
|
||||
// Error status
|
||||
pub const TXDESC_0_ES: u32 = 1 << 15;
|
||||
|
||||
// Transmit buffer size
|
||||
pub const TXDESC_1_TBS_SHIFT: usize = 0;
|
||||
pub const TXDESC_1_TBS_MASK: u32 = 0x0fff << TXDESC_1_TBS_SHIFT;
|
||||
}
|
||||
use tx_consts::*;
|
||||
|
||||
/// Transmit Descriptor representation
|
||||
///
|
||||
/// * tdes0: control
|
||||
/// * tdes1: buffer lengths
|
||||
/// * tdes2: data buffer address
|
||||
/// * tdes3: next descriptor address
|
||||
#[repr(C)]
|
||||
struct TDes {
|
||||
tdes0: VolatileCell<u32>,
|
||||
tdes1: VolatileCell<u32>,
|
||||
tdes2: VolatileCell<u32>,
|
||||
tdes3: VolatileCell<u32>,
|
||||
}
|
||||
|
||||
impl TDes {
|
||||
pub const fn new() -> Self {
|
||||
Self {
|
||||
tdes0: VolatileCell::new(0),
|
||||
tdes1: VolatileCell::new(0),
|
||||
tdes2: VolatileCell::new(0),
|
||||
tdes3: VolatileCell::new(0),
|
||||
}
|
||||
}
|
||||
|
||||
/// Return true if this TDes is not currently owned by the DMA
|
||||
pub fn available(&self) -> bool {
|
||||
(self.tdes0.get() & TXDESC_0_OWN) == 0
|
||||
}
|
||||
|
||||
/// Pass ownership to the DMA engine
|
||||
fn set_owned(&mut self) {
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
compiler_fence(Ordering::Release);
|
||||
self.tdes0.set(self.tdes0.get() | TXDESC_0_OWN);
|
||||
|
||||
// Used to flush the store buffer as fast as possible to make the buffer available for the
|
||||
// DMA.
|
||||
fence(Ordering::SeqCst);
|
||||
}
|
||||
|
||||
fn set_buffer1(&mut self, buffer: *const u8) {
|
||||
self.tdes2.set(buffer as u32);
|
||||
}
|
||||
|
||||
fn set_buffer1_len(&mut self, len: usize) {
|
||||
self.tdes1
|
||||
.set((self.tdes1.get() & !TXDESC_1_TBS_MASK) | ((len as u32) << TXDESC_1_TBS_SHIFT));
|
||||
}
|
||||
|
||||
// points to next descriptor (RCH)
|
||||
fn set_buffer2(&mut self, buffer: *const u8) {
|
||||
self.tdes3.set(buffer as u32);
|
||||
}
|
||||
|
||||
fn set_end_of_ring(&mut self) {
|
||||
self.tdes0.set(self.tdes0.get() | TXDESC_0_TER);
|
||||
}
|
||||
|
||||
// set up as a part fo the ring buffer - configures the tdes
|
||||
pub fn setup(&mut self, next: Option<&Self>) {
|
||||
// Defer this initialization to this function, so we can have `RingEntry` on bss.
|
||||
self.tdes0
|
||||
.set(TXDESC_0_TCH | TXDESC_0_IOC | TXDESC_0_FS | TXDESC_0_LS);
|
||||
match next {
|
||||
Some(next) => self.set_buffer2(next as *const TDes as *const u8),
|
||||
None => {
|
||||
self.set_buffer2(0 as *const u8);
|
||||
self.set_end_of_ring();
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) struct TDesRing<const N: usize> {
|
||||
descriptors: [TDes; N],
|
||||
buffers: [Option<PacketBuf>; N],
|
||||
next_entry: usize,
|
||||
}
|
||||
|
||||
impl<const N: usize> TDesRing<N> {
|
||||
pub const fn new() -> Self {
|
||||
const TDES: TDes = TDes::new();
|
||||
const BUFFERS: Option<PacketBuf> = None;
|
||||
|
||||
Self {
|
||||
descriptors: [TDES; N],
|
||||
buffers: [BUFFERS; N],
|
||||
next_entry: 0,
|
||||
}
|
||||
}
|
||||
|
||||
/// Initialise this TDesRing. Assume TDesRing is corrupt
|
||||
///
|
||||
/// The current memory address of the buffers inside this TDesRing
|
||||
/// will be stored in the descriptors, so ensure the TDesRing is
|
||||
/// not moved after initialisation.
|
||||
pub(crate) fn init(&mut self) {
|
||||
assert!(N > 0);
|
||||
|
||||
{
|
||||
let mut previous: Option<&mut TDes> = None;
|
||||
for entry in self.descriptors.iter_mut() {
|
||||
if let Some(prev) = &mut previous {
|
||||
prev.setup(Some(entry));
|
||||
}
|
||||
previous = Some(entry);
|
||||
}
|
||||
|
||||
if let Some(entry) = &mut previous {
|
||||
entry.setup(None);
|
||||
}
|
||||
}
|
||||
self.next_entry = 0;
|
||||
|
||||
// Register txdescriptor start
|
||||
// NOTE (unsafe) Used for atomic writes
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmatdlar()
|
||||
.write(|w| w.0 = &self.descriptors as *const _ as u32);
|
||||
}
|
||||
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
#[cfg(feature = "fence")]
|
||||
fence(Ordering::Release);
|
||||
|
||||
// We don't need a compiler fence here because all interactions with `Descriptor` are
|
||||
// volatiles
|
||||
|
||||
// Start transmission
|
||||
unsafe {
|
||||
ETH.ethernet_dma()
|
||||
.dmaomr()
|
||||
.modify(|w| w.set_st(St::STARTED))
|
||||
};
|
||||
}
|
||||
|
||||
/// Return true if a TDes is available for use
|
||||
pub(crate) fn available(&self) -> bool {
|
||||
self.descriptors[self.next_entry].available()
|
||||
}
|
||||
|
||||
pub(crate) fn transmit(&mut self, pkt: PacketBuf) -> Result<(), Error> {
|
||||
if !self.available() {
|
||||
return Err(Error::NoBufferAvailable);
|
||||
}
|
||||
|
||||
let descriptor = &mut self.descriptors[self.next_entry];
|
||||
|
||||
let pkt_len = pkt.len();
|
||||
let address = pkt.as_ptr() as *const u8;
|
||||
|
||||
descriptor.set_buffer1(address);
|
||||
descriptor.set_buffer1_len(pkt_len);
|
||||
|
||||
self.buffers[self.next_entry].replace(pkt);
|
||||
|
||||
descriptor.set_owned();
|
||||
|
||||
// Ensure changes to the descriptor are committed before DMA engine sees tail pointer store.
|
||||
// This will generate an DMB instruction.
|
||||
// "Preceding reads and writes cannot be moved past subsequent writes."
|
||||
fence(Ordering::Release);
|
||||
|
||||
// Move the tail pointer (TPR) to the next descriptor
|
||||
self.next_entry = (self.next_entry + 1) % N;
|
||||
|
||||
// Request the DMA engine to poll the latest tx descriptor
|
||||
unsafe { ETH.ethernet_dma().dmatpdr().modify(|w| w.0 = 1) }
|
||||
Ok(())
|
||||
}
|
||||
|
||||
pub(crate) fn on_interrupt(&mut self) -> Result<(), Error> {
|
||||
let previous = (self.next_entry + N - 1) % N;
|
||||
let td = &self.descriptors[previous];
|
||||
|
||||
// DMB to ensure that we are reading an updated value, probably not needed at the hardware
|
||||
// level, but this is also a hint to the compiler that we're syncing on the buffer.
|
||||
fence(Ordering::SeqCst);
|
||||
|
||||
let tdes0 = td.tdes0.get();
|
||||
|
||||
if tdes0 & TXDESC_0_OWN != 0 {
|
||||
// Transmission isn't done yet, probably a receive interrupt that fired this
|
||||
return Ok(());
|
||||
}
|
||||
|
||||
// Release the buffer
|
||||
self.buffers[previous].take();
|
||||
|
||||
if tdes0 & TXDESC_0_ES != 0 {
|
||||
Err(Error::TransmissionError)
|
||||
} else {
|
||||
Ok(())
|
||||
}
|
||||
}
|
||||
}
|
||||
Reference in New Issue
Block a user