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stm32: update metapac

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This commit is contained in:
xoviat 2023-10-20 20:21:53 -05:00
parent b1d0947a18
commit 0fb677aad7
9 changed files with 19 additions and 36 deletions
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4
embassy-stm32/Cargo.toml
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@ -58,7 +58,7 @@ rand_core = "0.6.3"
sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
critical-section = "1.1"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526" }
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-296dd041cce492e3b2b7fb3b8a6c05c9a34a90a1" }
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-5b04234fbe61ea875f1a904cd5f68795daaeb526", default-features = false, features = ["metadata"]}
stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-296dd041cce492e3b2b7fb3b8a6c05c9a34a90a1", default-features = false, features = ["metadata"]}
[features]

9
embassy-stm32/src/rcc/f1.rs
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@ -169,14 +169,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(not(rcc_f100))]
w.set_usbpre(Usbpre::from_bits(usbpre as u8));
w.set_sw(if pllmul_bits.is_some() {
#[cfg(not(rcc_f1cl))]
{
Sw::PLL1_P
}
#[cfg(rcc_f1cl)]
{
Sw::PLL
}
Sw::PLL1_P
} else if config.hse.is_some() {
Sw::HSE
} else {

3
embassy-stm32/src/rcc/l4l5.rs
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@ -189,9 +189,6 @@ pub(crate) unsafe fn init(config: Config) {
ClockSrc::HSE => hse.unwrap(),
ClockSrc::HSI => hsi16.unwrap(),
ClockSrc::MSI => msi.unwrap(),
#[cfg(rcc_l4)]
ClockSrc::PLL1_P => pll._r.unwrap(),
#[cfg(not(rcc_l4))]
ClockSrc::PLL1_R => pll._r.unwrap(),
};

4
embassy-stm32/src/rcc/u5.rs
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@ -92,7 +92,7 @@ impl Into<Pllsrc> for PllSrc {
match self {
PllSrc::MSIS(..) => Pllsrc::MSIS,
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI16 => Pllsrc::HSI16,
PllSrc::HSI16 => Pllsrc::HSI,
}
}
}
@ -102,7 +102,7 @@ impl Into<Sw> for ClockSrc {
match self {
ClockSrc::MSI(..) => Sw::MSIS,
ClockSrc::HSE(..) => Sw::HSE,
ClockSrc::HSI16 => Sw::HSI16,
ClockSrc::HSI16 => Sw::HSI,
ClockSrc::PLL1R(..) => Sw::PLL1_R,
}
}

14
embassy-stm32/src/rcc/wb.rs
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@ -59,7 +59,7 @@ pub const WPAN_DEFAULT: Config = Config {
frequency: mhz(32),
prediv: HsePrescaler::DIV1,
}),
sys: Sysclk::PLL,
sys: Sysclk::PLL1_R,
mux: Some(PllMux {
source: PllSource::HSE,
prediv: Pllm::DIV2,
@ -87,8 +87,8 @@ impl Default for Config {
#[inline]
fn default() -> Config {
Config {
sys: Sysclk::HSI,
hse: None,
sys: Sysclk::HSI16,
mux: None,
pll: None,
pllsai: None,
@ -113,7 +113,7 @@ pub(crate) unsafe fn init(config: Config) {
let mux_clk = config.mux.as_ref().map(|pll_mux| {
(match pll_mux.source {
PllSource::HSE => hse_clk.unwrap(),
PllSource::HSI16 => HSI_FREQ,
PllSource::HSI => HSI_FREQ,
_ => unreachable!(),
} / pll_mux.prediv)
});
@ -133,8 +133,8 @@ pub(crate) unsafe fn init(config: Config) {
let sys_clk = match config.sys {
Sysclk::HSE => hse_clk.unwrap(),
Sysclk::HSI16 => HSI_FREQ,
Sysclk::PLL => pll_r.unwrap(),
Sysclk::HSI => HSI_FREQ,
Sysclk::PLL1_R => pll_r.unwrap(),
_ => unreachable!(),
};
@ -161,12 +161,12 @@ pub(crate) unsafe fn init(config: Config) {
let rcc = crate::pac::RCC;
let needs_hsi = if let Some(pll_mux) = &config.mux {
pll_mux.source == PllSource::HSI16
pll_mux.source == PllSource::HSI
} else {
false
};
if needs_hsi || config.sys == Sysclk::HSI16 {
if needs_hsi || config.sys == Sysclk::HSI {
rcc.cr().modify(|w| {
w.set_hsion(true);
});

4
embassy-stm32/src/rcc/wba.rs
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@ -26,7 +26,7 @@ impl Into<Pllsrc> for PllSrc {
fn into(self) -> Pllsrc {
match self {
PllSrc::HSE(..) => Pllsrc::HSE,
PllSrc::HSI16 => Pllsrc::HSI16,
PllSrc::HSI16 => Pllsrc::HSI,
}
}
}
@ -35,7 +35,7 @@ impl Into<Sw> for ClockSrc {
fn into(self) -> Sw {
match self {
ClockSrc::HSE(..) => Sw::HSE,
ClockSrc::HSI16 => Sw::HSI16,
ClockSrc::HSI16 => Sw::HSI,
}
}
}

4
embassy-stm32/src/rcc/wl.rs
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@ -42,7 +42,7 @@ impl Default for Config {
shd_ahb_pre: AHBPrescaler::DIV1,
apb1_pre: APBPrescaler::DIV1,
apb2_pre: APBPrescaler::DIV1,
adc_clock_source: AdcClockSource::HSI16,
adc_clock_source: AdcClockSource::HSI,
ls: Default::default(),
}
}
@ -50,7 +50,7 @@ impl Default for Config {
pub(crate) unsafe fn init(config: Config) {
let (sys_clk, sw, vos) = match config.mux {
ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI16, VoltageScale::RANGE2),
ClockSrc::HSI16 => (HSI_FREQ, Sw::HSI, VoltageScale::RANGE2),
ClockSrc::HSE => (HSE_FREQ, Sw::HSE, VoltageScale::RANGE1),
ClockSrc::MSI(range) => (msirange_to_hertz(range), Sw::MSI, msirange_to_vos(range)),
};

4
embassy-stm32/src/sdmmc/mod.rs
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@ -1466,7 +1466,7 @@ cfg_if::cfg_if! {
(SDMMC1) => {
critical_section::with(|_| unsafe {
let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc1sel();
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
@ -1476,7 +1476,7 @@ cfg_if::cfg_if! {
(SDMMC2) => {
critical_section::with(|_| unsafe {
let sdmmcsel = crate::pac::RCC.dckcfgr2().read().sdmmc2sel();
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYS {
crate::rcc::get_freqs().sys
} else {
crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")

9
tests/stm32/src/common.rs
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@ -323,14 +323,7 @@ pub fn config() -> Config {
#[cfg(any(feature = "stm32l496zg", feature = "stm32l4a6zg", feature = "stm32l4r5zi"))]
{
use embassy_stm32::rcc::*;
#[cfg(feature = "stm32l4r5zi")]
{
config.rcc.mux = ClockSrc::PLL1_R;
}
#[cfg(not(feature = "stm32l4r5zi"))]
{
config.rcc.mux = ClockSrc::PLL1_P;
}
config.rcc.mux = ClockSrc::PLL1_R;
config.rcc.hsi16 = true;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI,