Convert files to LF endings.
This commit is contained in:
Dario Nieuwenhuis
parent
48957dce87
commit
10f5966787
@ -1,294 +1,294 @@
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//! Pulse Density Modulation (PDM) mirophone driver.
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#![macro_use]
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use futures::future::poll_fn;
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use crate::chip::EASY_DMA_SIZE;
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use crate::gpio::sealed::Pin;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::interrupt::typelevel::Interrupt;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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T::regs().intenclr.write(|w| w.end().clear());
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T::state().waker.wake();
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}
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}
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/// PDM microphone interface
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pub struct Pdm<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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}
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/// PDM error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Buffer is too long.
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BufferTooLong,
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/// Buffer is empty
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BufferZeroLength,
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/// PDM is not running
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NotRunning,
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}
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static DUMMY_BUFFER: [i16; 1] = [0; 1];
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impl<'d, T: Instance> Pdm<'d, T> {
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/// Create PDM driver
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pub fn new(
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pdm: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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clk: impl Peripheral<P = impl GpioPin> + 'd,
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din: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(pdm, clk, din);
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Self::new_inner(pdm, clk.map_into(), din.map_into(), config)
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}
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fn new_inner(
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pdm: PeripheralRef<'d, T>,
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clk: PeripheralRef<'d, AnyPin>,
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din: PeripheralRef<'d, AnyPin>,
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config: Config,
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) -> Self {
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into_ref!(pdm);
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let r = T::regs();
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// setup gpio pins
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din.conf().write(|w| w.input().set_bit());
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r.psel.din.write(|w| unsafe { w.bits(din.psel_bits()) });
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clk.set_low();
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clk.conf().write(|w| w.dir().output());
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r.psel.clk.write(|w| unsafe { w.bits(clk.psel_bits()) });
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// configure
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// use default for
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// - gain right
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// - gain left
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// - clk
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// - ratio
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r.mode.write(|w| {
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w.edge().bit(config.edge == Edge::LeftRising);
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w.operation().bit(config.operation_mode == OperationMode::Mono);
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w
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});
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r.gainl.write(|w| w.gainl().default_gain());
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r.gainr.write(|w| w.gainr().default_gain());
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// IRQ
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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r.enable.write(|w| w.enable().set_bit());
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Self { _peri: pdm }
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}
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/// Start sampling microphon data into a dummy buffer
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/// Usefull to start the microphon and keep it active between recording samples
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pub async fn start(&mut self) {
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let r = T::regs();
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// start dummy sampling because microphon needs some setup time
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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}
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/// Stop sampling microphon data inta a dummy buffer
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pub async fn stop(&mut self) {
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let r = T::regs();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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r.events_started.reset();
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}
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/// Sample data into the given buffer.
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pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let r = T::regs();
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if r.events_started.read().bits() == 0 {
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return Err(Error::NotRunning);
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}
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let drop = OnDrop::new(move || {
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r.intenclr.write(|w| w.end().clear());
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r.events_stopped.reset();
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// reset to dummy buffer
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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while r.events_stopped.read().bits() == 0 {}
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});
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// setup user buffer
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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r.sample.ptr.write(|w| unsafe { w.sampleptr().bits(ptr as u32) });
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r.sample.maxcnt.write(|w| unsafe { w.buffsize().bits(len as _) });
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// wait till the current sample is finished and the user buffer sample is started
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Self::wait_for_sample().await;
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// reset the buffer back to the dummy buffer
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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// wait till the user buffer is sampled
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Self::wait_for_sample().await;
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drop.defuse();
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Ok(())
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}
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async fn wait_for_sample() {
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let r = T::regs();
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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compiler_fence(Ordering::SeqCst);
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poll_fn(|cx| {
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T::state().waker.register(cx.waker());
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if r.events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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}
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}
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/// PDM microphone driver Config
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pub struct Config {
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/// Use stero or mono operation
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pub operation_mode: OperationMode,
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/// On which edge the left channel should be samples
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pub edge: Edge,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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operation_mode: OperationMode::Mono,
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edge: Edge::LeftFalling,
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}
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}
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}
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/// PDM operation mode.
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#[derive(PartialEq)]
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pub enum OperationMode {
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/// Mono (1 channel)
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Mono,
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/// Stereo (2 channels)
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Stereo,
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}
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/// PDM edge polarity
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#[derive(PartialEq)]
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pub enum Edge {
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/// Left edge is rising
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LeftRising,
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/// Left edge is falling
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LeftFalling,
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}
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impl<'d, T: Instance> Drop for Pdm<'d, T> {
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fn drop(&mut self) {
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let r = T::regs();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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r.enable.write(|w| w.enable().disabled());
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r.psel.din.reset();
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r.psel.clk.reset();
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}
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}
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pub(crate) mod sealed {
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use embassy_sync::waitqueue::AtomicWaker;
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/// Peripheral static state
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pub struct State {
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pub waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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}
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}
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}
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pub trait Instance {
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fn regs() -> &'static crate::pac::pdm::RegisterBlock;
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fn state() -> &'static State;
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}
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}
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/// PDM peripheral instance.
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pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
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/// Interrupt for this peripheral.
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type Interrupt: interrupt::typelevel::Interrupt;
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}
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macro_rules! impl_pdm {
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($type:ident, $pac_type:ident, $irq:ident) => {
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impl crate::pdm::sealed::Instance for peripherals::$type {
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fn regs() -> &'static crate::pac::pdm::RegisterBlock {
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unsafe { &*pac::$pac_type::ptr() }
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}
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fn state() -> &'static crate::pdm::sealed::State {
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static STATE: crate::pdm::sealed::State = crate::pdm::sealed::State::new();
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&STATE
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}
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}
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impl crate::pdm::Instance for peripherals::$type {
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type Interrupt = crate::interrupt::typelevel::$irq;
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}
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};
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}
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//! Pulse Density Modulation (PDM) mirophone driver.
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#![macro_use]
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use core::marker::PhantomData;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::Poll;
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use futures::future::poll_fn;
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use crate::chip::EASY_DMA_SIZE;
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use crate::gpio::sealed::Pin;
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use crate::gpio::{AnyPin, Pin as GpioPin};
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use crate::interrupt::typelevel::Interrupt;
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub struct InterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {
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T::regs().intenclr.write(|w| w.end().clear());
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T::state().waker.wake();
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}
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}
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/// PDM microphone interface
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pub struct Pdm<'d, T: Instance> {
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_peri: PeripheralRef<'d, T>,
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}
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/// PDM error.
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#[derive(Debug, Clone, Copy, PartialEq, Eq)]
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#[cfg_attr(feature = "defmt", derive(defmt::Format))]
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#[non_exhaustive]
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pub enum Error {
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/// Buffer is too long.
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BufferTooLong,
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/// Buffer is empty
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BufferZeroLength,
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/// PDM is not running
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NotRunning,
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}
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static DUMMY_BUFFER: [i16; 1] = [0; 1];
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impl<'d, T: Instance> Pdm<'d, T> {
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/// Create PDM driver
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pub fn new(
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pdm: impl Peripheral<P = T> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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clk: impl Peripheral<P = impl GpioPin> + 'd,
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din: impl Peripheral<P = impl GpioPin> + 'd,
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config: Config,
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) -> Self {
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into_ref!(pdm, clk, din);
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Self::new_inner(pdm, clk.map_into(), din.map_into(), config)
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}
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fn new_inner(
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pdm: PeripheralRef<'d, T>,
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clk: PeripheralRef<'d, AnyPin>,
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din: PeripheralRef<'d, AnyPin>,
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config: Config,
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) -> Self {
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into_ref!(pdm);
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let r = T::regs();
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// setup gpio pins
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din.conf().write(|w| w.input().set_bit());
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r.psel.din.write(|w| unsafe { w.bits(din.psel_bits()) });
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clk.set_low();
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clk.conf().write(|w| w.dir().output());
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r.psel.clk.write(|w| unsafe { w.bits(clk.psel_bits()) });
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// configure
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// use default for
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// - gain right
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// - gain left
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// - clk
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// - ratio
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r.mode.write(|w| {
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w.edge().bit(config.edge == Edge::LeftRising);
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w.operation().bit(config.operation_mode == OperationMode::Mono);
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w
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});
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r.gainl.write(|w| w.gainl().default_gain());
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r.gainr.write(|w| w.gainr().default_gain());
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// IRQ
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T::Interrupt::unpend();
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unsafe { T::Interrupt::enable() };
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r.enable.write(|w| w.enable().set_bit());
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Self { _peri: pdm }
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}
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/// Start sampling microphon data into a dummy buffer
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/// Usefull to start the microphon and keep it active between recording samples
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pub async fn start(&mut self) {
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let r = T::regs();
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// start dummy sampling because microphon needs some setup time
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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r.tasks_start.write(|w| unsafe { w.bits(1) });
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}
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/// Stop sampling microphon data inta a dummy buffer
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pub async fn stop(&mut self) {
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let r = T::regs();
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r.tasks_stop.write(|w| unsafe { w.bits(1) });
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r.events_started.reset();
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}
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/// Sample data into the given buffer.
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pub async fn sample(&mut self, buffer: &mut [i16]) -> Result<(), Error> {
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if buffer.len() == 0 {
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return Err(Error::BufferZeroLength);
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}
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if buffer.len() > EASY_DMA_SIZE {
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return Err(Error::BufferTooLong);
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}
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let r = T::regs();
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if r.events_started.read().bits() == 0 {
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return Err(Error::NotRunning);
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}
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let drop = OnDrop::new(move || {
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r.intenclr.write(|w| w.end().clear());
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r.events_stopped.reset();
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// reset to dummy buffer
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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while r.events_stopped.read().bits() == 0 {}
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});
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// setup user buffer
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let ptr = buffer.as_ptr();
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let len = buffer.len();
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r.sample.ptr.write(|w| unsafe { w.sampleptr().bits(ptr as u32) });
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r.sample.maxcnt.write(|w| unsafe { w.buffsize().bits(len as _) });
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// wait till the current sample is finished and the user buffer sample is started
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Self::wait_for_sample().await;
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// reset the buffer back to the dummy buffer
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r.sample
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.ptr
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.write(|w| unsafe { w.sampleptr().bits(DUMMY_BUFFER.as_ptr() as u32) });
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r.sample
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.maxcnt
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.write(|w| unsafe { w.buffsize().bits(DUMMY_BUFFER.len() as _) });
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// wait till the user buffer is sampled
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Self::wait_for_sample().await;
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drop.defuse();
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Ok(())
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}
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async fn wait_for_sample() {
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let r = T::regs();
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r.events_end.reset();
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r.intenset.write(|w| w.end().set());
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compiler_fence(Ordering::SeqCst);
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poll_fn(|cx| {
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T::state().waker.register(cx.waker());
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if r.events_end.read().bits() != 0 {
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return Poll::Ready(());
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}
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Poll::Pending
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})
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.await;
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compiler_fence(Ordering::SeqCst);
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}
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}
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/// PDM microphone driver Config
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pub struct Config {
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/// Use stero or mono operation
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pub operation_mode: OperationMode,
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/// On which edge the left channel should be samples
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pub edge: Edge,
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}
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impl Default for Config {
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fn default() -> Self {
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Self {
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operation_mode: OperationMode::Mono,
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edge: Edge::LeftFalling,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
/// PDM operation mode.
|
||||
#[derive(PartialEq)]
|
||||
pub enum OperationMode {
|
||||
/// Mono (1 channel)
|
||||
Mono,
|
||||
/// Stereo (2 channels)
|
||||
Stereo,
|
||||
}
|
||||
|
||||
/// PDM edge polarity
|
||||
#[derive(PartialEq)]
|
||||
pub enum Edge {
|
||||
/// Left edge is rising
|
||||
LeftRising,
|
||||
/// Left edge is falling
|
||||
LeftFalling,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance> Drop for Pdm<'d, T> {
|
||||
fn drop(&mut self) {
|
||||
let r = T::regs();
|
||||
|
||||
r.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
|
||||
r.enable.write(|w| w.enable().disabled());
|
||||
|
||||
r.psel.din.reset();
|
||||
r.psel.clk.reset();
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use embassy_sync::waitqueue::AtomicWaker;
|
||||
|
||||
/// Peripheral static state
|
||||
pub struct State {
|
||||
pub waker: AtomicWaker,
|
||||
}
|
||||
|
||||
impl State {
|
||||
pub const fn new() -> Self {
|
||||
Self {
|
||||
waker: AtomicWaker::new(),
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance {
|
||||
fn regs() -> &'static crate::pac::pdm::RegisterBlock;
|
||||
fn state() -> &'static State;
|
||||
}
|
||||
}
|
||||
|
||||
/// PDM peripheral instance.
|
||||
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
|
||||
/// Interrupt for this peripheral.
|
||||
type Interrupt: interrupt::typelevel::Interrupt;
|
||||
}
|
||||
|
||||
macro_rules! impl_pdm {
|
||||
($type:ident, $pac_type:ident, $irq:ident) => {
|
||||
impl crate::pdm::sealed::Instance for peripherals::$type {
|
||||
fn regs() -> &'static crate::pac::pdm::RegisterBlock {
|
||||
unsafe { &*pac::$pac_type::ptr() }
|
||||
}
|
||||
fn state() -> &'static crate::pdm::sealed::State {
|
||||
static STATE: crate::pdm::sealed::State = crate::pdm::sealed::State::new();
|
||||
&STATE
|
||||
}
|
||||
}
|
||||
impl crate::pdm::Instance for peripherals::$type {
|
||||
type Interrupt = crate::interrupt::typelevel::$irq;
|
||||
}
|
||||
};
|
||||
}
|
||||
|
||||
@ -1,332 +1,332 @@
|
||||
#![macro_use]
|
||||
|
||||
pub mod enums;
|
||||
|
||||
use embassy_hal_common::{into_ref, PeripheralRef};
|
||||
use enums::*;
|
||||
|
||||
use crate::dma::Transfer;
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::AnyPin;
|
||||
use crate::pac::quadspi::Quadspi as Regs;
|
||||
use crate::rcc::RccPeripheral;
|
||||
use crate::{peripherals, Peripheral};
|
||||
|
||||
pub struct TransferConfig {
|
||||
/// Instraction width (IMODE)
|
||||
pub iwidth: QspiWidth,
|
||||
/// Address width (ADMODE)
|
||||
pub awidth: QspiWidth,
|
||||
/// Data width (DMODE)
|
||||
pub dwidth: QspiWidth,
|
||||
/// Instruction Id
|
||||
pub instruction: u8,
|
||||
/// Flash memory address
|
||||
pub address: Option<u32>,
|
||||
/// Number of dummy cycles (DCYC)
|
||||
pub dummy: DummyCycles,
|
||||
/// Length of data
|
||||
pub data_len: Option<usize>,
|
||||
}
|
||||
|
||||
impl Default for TransferConfig {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
iwidth: QspiWidth::NONE,
|
||||
awidth: QspiWidth::NONE,
|
||||
dwidth: QspiWidth::NONE,
|
||||
instruction: 0,
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
data_len: None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Config {
|
||||
/// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
|
||||
/// If you need other value the whose predefined use `Other` variant.
|
||||
pub memory_size: MemorySize,
|
||||
/// Address size (8/16/24/32-bit)
|
||||
pub address_size: AddressSize,
|
||||
/// Scalar factor for generating CLK [0-255]
|
||||
pub prescaler: u8,
|
||||
/// Number of bytes to trigger FIFO threshold flag.
|
||||
pub fifo_threshold: FIFOThresholdLevel,
|
||||
/// Minimum number of cycles that chip select must be high between issued commands
|
||||
pub cs_high_time: ChipSelectHightTime,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
memory_size: MemorySize::Other(0),
|
||||
address_size: AddressSize::_24bit,
|
||||
prescaler: 128,
|
||||
fifo_threshold: FIFOThresholdLevel::_17Bytes,
|
||||
cs_high_time: ChipSelectHightTime::_5Cycle,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
pub struct Qspi<'d, T: Instance, Dma> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
nss: Option<PeripheralRef<'d, AnyPin>>,
|
||||
dma: PeripheralRef<'d, Dma>,
|
||||
config: Config,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
|
||||
pub fn new(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
||||
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
||||
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
|
||||
d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
|
||||
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
||||
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, d0, d1, d2, d3, sck, nss);
|
||||
|
||||
sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
|
||||
sck.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
|
||||
nss.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
|
||||
d0.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
|
||||
d1.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
|
||||
d2.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
|
||||
d3.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
Self::new_inner(
|
||||
peri,
|
||||
Some(d0.map_into()),
|
||||
Some(d1.map_into()),
|
||||
Some(d2.map_into()),
|
||||
Some(d3.map_into()),
|
||||
Some(sck.map_into()),
|
||||
Some(nss.map_into()),
|
||||
dma,
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
d0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
nss: Option<PeripheralRef<'d, AnyPin>>,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, dma);
|
||||
|
||||
T::enable();
|
||||
T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into()));
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
T::REGS.cr().write(|w| {
|
||||
w.set_prescaler(config.prescaler);
|
||||
w.set_en(true);
|
||||
});
|
||||
T::REGS.dcr().write(|w| {
|
||||
w.set_fsize(config.memory_size.into());
|
||||
w.set_csht(config.cs_high_time.into());
|
||||
w.set_ckmode(false);
|
||||
});
|
||||
|
||||
Self {
|
||||
_peri: peri,
|
||||
sck,
|
||||
d0,
|
||||
d1,
|
||||
d2,
|
||||
d3,
|
||||
nss,
|
||||
dma,
|
||||
config,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn command(&mut self, transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
|
||||
buf[idx] = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() };
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().ftf() {}
|
||||
unsafe { (T::REGS.dr().as_ptr() as *mut u8).write_volatile(buf[idx]) };
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
let request = self.dma.request();
|
||||
let transfer = unsafe {
|
||||
Transfer::new_read(
|
||||
&mut self.dma,
|
||||
request,
|
||||
T::REGS.dr().as_ptr() as *mut u8,
|
||||
buf,
|
||||
Default::default(),
|
||||
)
|
||||
};
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
transfer.blocking_wait();
|
||||
}
|
||||
|
||||
pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
let request = self.dma.request();
|
||||
let transfer = unsafe {
|
||||
Transfer::new_write(
|
||||
&mut self.dma,
|
||||
request,
|
||||
buf,
|
||||
T::REGS.dr().as_ptr() as *mut u8,
|
||||
Default::default(),
|
||||
)
|
||||
};
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
transfer.blocking_wait();
|
||||
}
|
||||
|
||||
fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig) {
|
||||
T::REGS.fcr().modify(|v| {
|
||||
v.set_csmf(true);
|
||||
v.set_ctcf(true);
|
||||
v.set_ctef(true);
|
||||
v.set_ctof(true);
|
||||
});
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
|
||||
}
|
||||
|
||||
T::REGS.ccr().write(|v| {
|
||||
v.set_fmode(fmode.into());
|
||||
v.set_imode(transaction.iwidth.into());
|
||||
v.set_instruction(transaction.instruction);
|
||||
v.set_admode(transaction.awidth.into());
|
||||
v.set_adsize(self.config.address_size.into());
|
||||
v.set_dmode(transaction.dwidth.into());
|
||||
v.set_abmode(QspiWidth::NONE.into());
|
||||
v.set_dcyc(transaction.dummy.into());
|
||||
});
|
||||
|
||||
if let Some(addr) = transaction.address {
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(addr);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Instance {
|
||||
const REGS: Regs;
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
|
||||
|
||||
pin_trait!(SckPin, Instance);
|
||||
pin_trait!(D0Pin, Instance);
|
||||
pin_trait!(D1Pin, Instance);
|
||||
pin_trait!(D2Pin, Instance);
|
||||
pin_trait!(D3Pin, Instance);
|
||||
pin_trait!(NSSPin, Instance);
|
||||
|
||||
dma_trait!(QuadDma, Instance);
|
||||
|
||||
foreach_peripheral!(
|
||||
(quadspi, $inst:ident) => {
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
const REGS: Regs = crate::pac::$inst;
|
||||
}
|
||||
|
||||
impl Instance for peripherals::$inst {}
|
||||
};
|
||||
);
|
||||
#![macro_use]
|
||||
|
||||
pub mod enums;
|
||||
|
||||
use embassy_hal_common::{into_ref, PeripheralRef};
|
||||
use enums::*;
|
||||
|
||||
use crate::dma::Transfer;
|
||||
use crate::gpio::sealed::AFType;
|
||||
use crate::gpio::AnyPin;
|
||||
use crate::pac::quadspi::Quadspi as Regs;
|
||||
use crate::rcc::RccPeripheral;
|
||||
use crate::{peripherals, Peripheral};
|
||||
|
||||
pub struct TransferConfig {
|
||||
/// Instraction width (IMODE)
|
||||
pub iwidth: QspiWidth,
|
||||
/// Address width (ADMODE)
|
||||
pub awidth: QspiWidth,
|
||||
/// Data width (DMODE)
|
||||
pub dwidth: QspiWidth,
|
||||
/// Instruction Id
|
||||
pub instruction: u8,
|
||||
/// Flash memory address
|
||||
pub address: Option<u32>,
|
||||
/// Number of dummy cycles (DCYC)
|
||||
pub dummy: DummyCycles,
|
||||
/// Length of data
|
||||
pub data_len: Option<usize>,
|
||||
}
|
||||
|
||||
impl Default for TransferConfig {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
iwidth: QspiWidth::NONE,
|
||||
awidth: QspiWidth::NONE,
|
||||
dwidth: QspiWidth::NONE,
|
||||
instruction: 0,
|
||||
address: None,
|
||||
dummy: DummyCycles::_0,
|
||||
data_len: None,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub struct Config {
|
||||
/// Flash memory size representend as 2^[0-32], as reasonable minimum 1KiB(9) was chosen.
|
||||
/// If you need other value the whose predefined use `Other` variant.
|
||||
pub memory_size: MemorySize,
|
||||
/// Address size (8/16/24/32-bit)
|
||||
pub address_size: AddressSize,
|
||||
/// Scalar factor for generating CLK [0-255]
|
||||
pub prescaler: u8,
|
||||
/// Number of bytes to trigger FIFO threshold flag.
|
||||
pub fifo_threshold: FIFOThresholdLevel,
|
||||
/// Minimum number of cycles that chip select must be high between issued commands
|
||||
pub cs_high_time: ChipSelectHightTime,
|
||||
}
|
||||
|
||||
impl Default for Config {
|
||||
fn default() -> Self {
|
||||
Self {
|
||||
memory_size: MemorySize::Other(0),
|
||||
address_size: AddressSize::_24bit,
|
||||
prescaler: 128,
|
||||
fifo_threshold: FIFOThresholdLevel::_17Bytes,
|
||||
cs_high_time: ChipSelectHightTime::_5Cycle,
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
#[allow(dead_code)]
|
||||
pub struct Qspi<'d, T: Instance, Dma> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
nss: Option<PeripheralRef<'d, AnyPin>>,
|
||||
dma: PeripheralRef<'d, Dma>,
|
||||
config: Config,
|
||||
}
|
||||
|
||||
impl<'d, T: Instance, Dma> Qspi<'d, T, Dma> {
|
||||
pub fn new(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
|
||||
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
|
||||
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
|
||||
d3: impl Peripheral<P = impl D3Pin<T>> + 'd,
|
||||
sck: impl Peripheral<P = impl SckPin<T>> + 'd,
|
||||
nss: impl Peripheral<P = impl NSSPin<T>> + 'd,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, d0, d1, d2, d3, sck, nss);
|
||||
|
||||
sck.set_as_af(sck.af_num(), AFType::OutputPushPull);
|
||||
sck.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
nss.set_as_af(nss.af_num(), AFType::OutputPushPull);
|
||||
nss.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d0.set_as_af(d0.af_num(), AFType::OutputPushPull);
|
||||
d0.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d1.set_as_af(d1.af_num(), AFType::OutputPushPull);
|
||||
d1.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d2.set_as_af(d2.af_num(), AFType::OutputPushPull);
|
||||
d2.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
d3.set_as_af(d3.af_num(), AFType::OutputPushPull);
|
||||
d3.set_speed(crate::gpio::Speed::VeryHigh);
|
||||
|
||||
Self::new_inner(
|
||||
peri,
|
||||
Some(d0.map_into()),
|
||||
Some(d1.map_into()),
|
||||
Some(d2.map_into()),
|
||||
Some(d3.map_into()),
|
||||
Some(sck.map_into()),
|
||||
Some(nss.map_into()),
|
||||
dma,
|
||||
config,
|
||||
)
|
||||
}
|
||||
|
||||
fn new_inner(
|
||||
peri: impl Peripheral<P = T> + 'd,
|
||||
d0: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d1: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d2: Option<PeripheralRef<'d, AnyPin>>,
|
||||
d3: Option<PeripheralRef<'d, AnyPin>>,
|
||||
sck: Option<PeripheralRef<'d, AnyPin>>,
|
||||
nss: Option<PeripheralRef<'d, AnyPin>>,
|
||||
dma: impl Peripheral<P = Dma> + 'd,
|
||||
config: Config,
|
||||
) -> Self {
|
||||
into_ref!(peri, dma);
|
||||
|
||||
T::enable();
|
||||
T::REGS.cr().write(|w| w.set_fthres(config.fifo_threshold.into()));
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
T::REGS.cr().write(|w| {
|
||||
w.set_prescaler(config.prescaler);
|
||||
w.set_en(true);
|
||||
});
|
||||
T::REGS.dcr().write(|w| {
|
||||
w.set_fsize(config.memory_size.into());
|
||||
w.set_csht(config.cs_high_time.into());
|
||||
w.set_ckmode(false);
|
||||
});
|
||||
|
||||
Self {
|
||||
_peri: peri,
|
||||
sck,
|
||||
d0,
|
||||
d1,
|
||||
d2,
|
||||
d3,
|
||||
nss,
|
||||
dma,
|
||||
config,
|
||||
}
|
||||
}
|
||||
|
||||
pub fn command(&mut self, transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_read(&mut self, buf: &mut [u8], transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().tcf() && !T::REGS.sr().read().ftf() {}
|
||||
buf[idx] = unsafe { (T::REGS.dr().as_ptr() as *mut u8).read_volatile() };
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_write(&mut self, buf: &[u8], transaction: TransferConfig) {
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(false));
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
for idx in 0..len {
|
||||
while !T::REGS.sr().read().ftf() {}
|
||||
unsafe { (T::REGS.dr().as_ptr() as *mut u8).write_volatile(buf[idx]) };
|
||||
}
|
||||
}
|
||||
|
||||
while !T::REGS.sr().read().tcf() {}
|
||||
T::REGS.fcr().modify(|v| v.set_ctcf(true));
|
||||
}
|
||||
|
||||
pub fn blocking_read_dma(&mut self, buf: &mut [u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectRead.into());
|
||||
});
|
||||
let current_ar = T::REGS.ar().read().address();
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(current_ar);
|
||||
});
|
||||
|
||||
let request = self.dma.request();
|
||||
let transfer = unsafe {
|
||||
Transfer::new_read(
|
||||
&mut self.dma,
|
||||
request,
|
||||
T::REGS.dr().as_ptr() as *mut u8,
|
||||
buf,
|
||||
Default::default(),
|
||||
)
|
||||
};
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
transfer.blocking_wait();
|
||||
}
|
||||
|
||||
pub fn blocking_write_dma(&mut self, buf: &[u8], transaction: TransferConfig)
|
||||
where
|
||||
Dma: QuadDma<T>,
|
||||
{
|
||||
self.setup_transaction(QspiMode::IndirectWrite, &transaction);
|
||||
|
||||
T::REGS.ccr().modify(|v| {
|
||||
v.set_fmode(QspiMode::IndirectWrite.into());
|
||||
});
|
||||
|
||||
let request = self.dma.request();
|
||||
let transfer = unsafe {
|
||||
Transfer::new_write(
|
||||
&mut self.dma,
|
||||
request,
|
||||
buf,
|
||||
T::REGS.dr().as_ptr() as *mut u8,
|
||||
Default::default(),
|
||||
)
|
||||
};
|
||||
|
||||
T::REGS.cr().modify(|v| v.set_dmaen(true));
|
||||
|
||||
transfer.blocking_wait();
|
||||
}
|
||||
|
||||
fn setup_transaction(&mut self, fmode: QspiMode, transaction: &TransferConfig) {
|
||||
T::REGS.fcr().modify(|v| {
|
||||
v.set_csmf(true);
|
||||
v.set_ctcf(true);
|
||||
v.set_ctef(true);
|
||||
v.set_ctof(true);
|
||||
});
|
||||
|
||||
while T::REGS.sr().read().busy() {}
|
||||
|
||||
if let Some(len) = transaction.data_len {
|
||||
T::REGS.dlr().write(|v| v.set_dl(len as u32 - 1));
|
||||
}
|
||||
|
||||
T::REGS.ccr().write(|v| {
|
||||
v.set_fmode(fmode.into());
|
||||
v.set_imode(transaction.iwidth.into());
|
||||
v.set_instruction(transaction.instruction);
|
||||
v.set_admode(transaction.awidth.into());
|
||||
v.set_adsize(self.config.address_size.into());
|
||||
v.set_dmode(transaction.dwidth.into());
|
||||
v.set_abmode(QspiWidth::NONE.into());
|
||||
v.set_dcyc(transaction.dummy.into());
|
||||
});
|
||||
|
||||
if let Some(addr) = transaction.address {
|
||||
T::REGS.ar().write(|v| {
|
||||
v.set_address(addr);
|
||||
});
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
pub(crate) mod sealed {
|
||||
use super::*;
|
||||
|
||||
pub trait Instance {
|
||||
const REGS: Regs;
|
||||
}
|
||||
}
|
||||
|
||||
pub trait Instance: Peripheral<P = Self> + sealed::Instance + RccPeripheral {}
|
||||
|
||||
pin_trait!(SckPin, Instance);
|
||||
pin_trait!(D0Pin, Instance);
|
||||
pin_trait!(D1Pin, Instance);
|
||||
pin_trait!(D2Pin, Instance);
|
||||
pin_trait!(D3Pin, Instance);
|
||||
pin_trait!(NSSPin, Instance);
|
||||
|
||||
dma_trait!(QuadDma, Instance);
|
||||
|
||||
foreach_peripheral!(
|
||||
(quadspi, $inst:ident) => {
|
||||
impl sealed::Instance for peripherals::$inst {
|
||||
const REGS: Regs = crate::pac::$inst;
|
||||
}
|
||||
|
||||
impl Instance for peripherals::$inst {}
|
||||
};
|
||||
);
|
||||
|
||||
Loading…
Reference in New Issue
Block a user