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STM32H7: Ethernet: Disable RA in MAC filtering, fix order of MACA0 register writes.

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Adam Greig 2021-09-06 23:16:43 +01:00
parent 2928b99218
commit 14fa6c2760
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GPG Key ID: 8B3FE5477B1DD9A0
1 changed files with 4 additions and 3 deletions
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7
embassy-stm32/src/eth/v2/mod.rs
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@ -98,6 +98,10 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
// TODO: Carrier sense ? ECRSFD // TODO: Carrier sense ? ECRSFD
}); });
// Note: Writing to LR triggers synchronisation of both LR and HR into the MAC core,
// so the LR write must happen after the HR write.
mac.maca0hr()
.modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
mac.maca0lr().write(|w| { mac.maca0lr().write(|w| {
w.set_addrlo( w.set_addrlo(
u32::from(mac_addr[0]) u32::from(mac_addr[0])
@ -106,10 +110,7 @@ impl<'d, P: PHY, const TX: usize, const RX: usize> Ethernet<'d, P, TX, RX> {
| (u32::from(mac_addr[3]) << 24), | (u32::from(mac_addr[3]) << 24),
) )
}); });
mac.maca0hr()
.modify(|w| w.set_addrhi(u16::from(mac_addr[4]) | (u16::from(mac_addr[5]) << 8)));
mac.macpfr().modify(|w| w.set_ra(true));
mac.macqtx_fcr().modify(|w| w.set_pt(0x100)); mac.macqtx_fcr().modify(|w| w.set_pt(0x100));
mtl.mtlrx_qomr().modify(|w| w.set_rsf(true)); mtl.mtlrx_qomr().modify(|w| w.set_rsf(true));