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Merge pull request #1347 from embassy-rs/h5-spi

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stm32h5: add spi support, fix DMA hang, add HIL tests.
This commit is contained in:
Dario Nieuwenhuis
2023-04-10 21:27:44 +02:00
committed by GitHub
parent 53c60df997 cae683cd41
commit 1f25d2ba83
10 changed files with 83 additions and 56 deletions
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4
embassy-stm32/Cargo.toml
View File

@ -58,7 +58,7 @@ sdio-host = "0.5.0"
embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "46d1b1c2ff13e31e282ec1e352421721694f126a", optional = true }
critical-section = "1.1"
atomic-polyfill = "1.0.1"
stm32-metapac = "4"
stm32-metapac = "5"
vcell = "0.1.3"
bxcan = "0.7.0"
nb = "1.0.0"
@ -73,7 +73,7 @@ critical-section = { version = "1.1", features = ["std"] }
[build-dependencies]
proc-macro2 = "1.0.36"
quote = "1.0.15"
stm32-metapac = { version = "4", default-features = false, features = ["metadata"]}
stm32-metapac = { version = "5", default-features = false, features = ["metadata"]}
[features]
default = ["stm32-metapac/rt"]

11
embassy-stm32/src/dma/gpdma.rs
View File

@ -190,6 +190,10 @@ mod low_level_api {
fence(Ordering::SeqCst);
let ch = dma.ch(channel_number as _);
// Reset ch
ch.cr().write(|w| w.set_reset(true));
ch.llr().write(|_| {}); // no linked list
ch.tr1().write(|w| {
w.set_sdw(data_size.into());
@ -252,7 +256,7 @@ mod low_level_api {
/// Gets the running status of the channel
pub unsafe fn is_running(dma: Gpdma, ch: u8) -> bool {
let ch = dma.ch(ch as _);
!ch.sr().read().idlef()
!ch.sr().read().tcf()
}
/// Gets the total remaining transfers for the channel
@ -291,7 +295,10 @@ mod low_level_api {
}
if sr.suspf() || sr.tcf() {
ch.cr().write(|w| w.set_reset(true));
// disable all xxIEs to prevent the irq from firing again.
ch.cr().write(|_| {});
// Wake the future. It'll look at tcf and see it's set.
STATE.channels[state_index].waker.wake();
}
}

72
embassy-stm32/src/spi/mod.rs
View File

@ -258,7 +258,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_spe(true);
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.ifcr().write(|w| w.0 = 0xffff_ffff);
T::REGS.cfg2().modify(|w| {
@ -317,7 +317,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.cfg2().modify(|w| {
w.set_cpha(cpha);
@ -330,7 +330,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
pub fn get_current_config(&self) -> Config {
#[cfg(any(spi_v1, spi_f1, spi_v2))]
let cfg = unsafe { T::REGS.cr1().read() };
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let cfg = unsafe { T::REGS.cfg2().read() };
let polarity = if cfg.cpol() == vals::Cpol::IDLELOW {
Polarity::IdleLow
@ -383,7 +383,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
w.set_spe(true);
});
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
unsafe {
T::REGS.cr1().modify(|w| {
w.set_csusp(true);
@ -429,7 +429,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -459,7 +459,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
// SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
@ -481,7 +481,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -514,7 +514,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
}
// SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
@ -534,7 +534,7 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| {
w.set_spe(true);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
T::REGS.cr1().modify(|w| {
w.set_cstart(true);
});
@ -619,9 +619,9 @@ impl<'d, T: Instance, Tx, Rx> Drop for Spi<'d, T, Tx, Rx> {
}
}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
use vals::Br;
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
use vals::Mbr as Br;
fn compute_baud_rate(clocks: Hertz, freq: Hertz) -> Br {
@ -647,17 +647,17 @@ trait RegsExt {
impl RegsExt for Regs {
fn tx_ptr<W>(&self) -> *mut W {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
let dr = self.dr();
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let dr = self.txdr();
dr.ptr() as *mut W
}
fn rx_ptr<W>(&self) -> *mut W {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
let dr = self.dr();
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
let dr = self.rxdr();
dr.ptr() as *mut W
}
@ -667,22 +667,22 @@ fn check_error_flags(sr: regs::Sr) -> Result<(), Error> {
if sr.ovr() {
return Err(Error::Overrun);
}
#[cfg(not(any(spi_f1, spi_v3, spi_v4)))]
#[cfg(not(any(spi_f1, spi_v3, spi_v4, spi_v5)))]
if sr.fre() {
return Err(Error::Framing);
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.tifre() {
return Err(Error::Framing);
}
if sr.modf() {
return Err(Error::ModeFault);
}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.crcerr() {
return Err(Error::Crc);
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.crce() {
return Err(Error::Crc);
}
@ -696,11 +696,11 @@ fn spin_until_tx_ready(regs: Regs) -> Result<(), Error> {
check_error_flags(sr)?;
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.txe() {
return Ok(());
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.txp() {
return Ok(());
}
@ -713,11 +713,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
check_error_flags(sr)?;
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
if sr.rxne() {
return Ok(());
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
if sr.rxp() {
return Ok(());
}
@ -726,11 +726,11 @@ fn spin_until_rx_ready(regs: Regs) -> Result<(), Error> {
fn flush_rx_fifo(regs: Regs) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
while regs.sr().read().rxne() {
let _ = regs.dr().read();
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
while regs.sr().read().rxp() {
let _ = regs.rxdr().read();
}
@ -739,11 +739,11 @@ fn flush_rx_fifo(regs: Regs) {
fn set_txdmaen(regs: Regs, val: bool) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_txdmaen(val);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_txdmaen(val);
});
@ -752,11 +752,11 @@ fn set_txdmaen(regs: Regs, val: bool) {
fn set_rxdmaen(regs: Regs, val: bool) {
unsafe {
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_rxdmaen(val);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_rxdmaen(val);
});
@ -768,9 +768,9 @@ fn finish_dma(regs: Regs) {
#[cfg(spi_v2)]
while regs.sr().read().ftlvl() > 0 {}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
while !regs.sr().read().txc() {}
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
while regs.sr().read().bsy() {}
// Disable the spi peripheral
@ -780,12 +780,12 @@ fn finish_dma(regs: Regs) {
// The peripheral automatically disables the DMA stream on completion without error,
// but it does not clear the RXDMAEN/TXDMAEN flag in CR2.
#[cfg(not(any(spi_v3, spi_v4)))]
#[cfg(not(any(spi_v3, spi_v4, spi_v5)))]
regs.cr2().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
});
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cfg1().modify(|reg| {
reg.set_txdmaen(false);
reg.set_rxdmaen(false);
@ -799,7 +799,7 @@ fn transfer_word<W: Word>(regs: Regs, tx_word: W) -> Result<W, Error> {
unsafe {
ptr::write_volatile(regs.tx_ptr(), tx_word);
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
regs.cr1().modify(|reg| reg.set_cstart(true));
}
@ -970,7 +970,7 @@ pub(crate) mod sealed {
}
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
pub fn dsize(&self) -> u8 {
match self {
WordSize::EightBit => 0b0111,
@ -978,7 +978,7 @@ pub(crate) mod sealed {
}
}
#[cfg(any(spi_v3, spi_v4))]
#[cfg(any(spi_v3, spi_v4, spi_v5))]
pub fn _frxth(&self) -> vals::Fthlv {
match self {
WordSize::EightBit => vals::Fthlv::ONEFRAME,