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rcc: update pll clock naming

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This commit is contained in:
xoviat 2023-10-15 15:10:42 -05:00
parent cd92bc3145
commit 1fc35c753b
6 changed files with 22 additions and 17 deletions
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2
embassy-stm32/src/i2s.rs
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@ -170,7 +170,7 @@ impl<'d, T: Instance, Tx, Rx> I2S<'d, T, Tx, Rx> {
let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg); let spi = Spi::new_internal(peri, txdma, rxdma, spi_cfg);
#[cfg(all(rcc_f4, not(stm32f410)))] #[cfg(all(rcc_f4, not(stm32f410)))]
let pclk = unsafe { get_freqs() }.plli2s.unwrap(); let pclk = unsafe { get_freqs() }.plli2s1_q.unwrap();
#[cfg(stm32f410)] #[cfg(stm32f410)]
let pclk = T::frequency(); let pclk = T::frequency();

2
embassy-stm32/src/rcc/f2.rs
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@ -314,7 +314,7 @@ pub(crate) unsafe fn init(config: Config) {
apb1_tim: apb1_tim_freq, apb1_tim: apb1_tim_freq,
apb2: apb2_freq, apb2: apb2_freq,
apb2_tim: apb2_tim_freq, apb2_tim: apb2_tim_freq,
pll48: Some(pll_clocks.pll48_freq), pll1_q: Some(pll_clocks.pll48_freq),
rtc, rtc,
}); });
} }

10
embassy-stm32/src/rcc/f4.rs
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@ -350,13 +350,17 @@ pub(crate) unsafe fn init(config: Config) {
ahb2: Hertz(hclk), ahb2: Hertz(hclk),
ahb3: Hertz(hclk), ahb3: Hertz(hclk),
pll48: plls.pll48clk.map(Hertz), pll1_q: plls.pll48clk.map(Hertz),
#[cfg(not(stm32f410))] #[cfg(not(stm32f410))]
plli2s: plls.plli2sclk.map(Hertz), plli2s1_q: plls.plli2sclk.map(Hertz),
#[cfg(not(stm32f410))]
plli2s1_r: None,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pllsai: plls.pllsaiclk.map(Hertz), pllsai1_q: plls.pllsaiclk.map(Hertz),
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pllsai1_r: None,
rtc, rtc,
}); });

2
embassy-stm32/src/rcc/f7.rs
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@ -269,7 +269,7 @@ pub(crate) unsafe fn init(config: Config) {
ahb2: Hertz(hclk), ahb2: Hertz(hclk),
ahb3: Hertz(hclk), ahb3: Hertz(hclk),
pll48: plls.pll48clk.map(Hertz), pll1_q: plls.pll48clk.map(Hertz),
rtc, rtc,
}); });

17
embassy-stm32/src/rcc/mod.rs
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@ -104,24 +104,25 @@ pub struct Clocks {
#[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))] #[cfg(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab, rcc_wba))]
pub ahb4: Hertz, pub ahb4: Hertz,
#[cfg(any(rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
pub pll48: Option<Hertz>,
#[cfg(all(rcc_f4, not(stm32f410)))] #[cfg(all(rcc_f4, not(stm32f410)))]
pub plli2s: Option<Hertz>, pub plli2s1_q: Option<Hertz>,
#[cfg(all(rcc_f4, not(stm32f410)))]
pub plli2s1_r: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))] #[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai: Option<Hertz>, pub pllsai1_q: Option<Hertz>,
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai1_r: Option<Hertz>,
#[cfg(stm32g4)] #[cfg(stm32g4)]
pub pll1_p: Option<Hertz>, pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))] #[cfg(any(stm32h5, stm32h7, rcc_f2, rcc_f4, rcc_f410, rcc_f7))]
pub pll1_q: Option<Hertz>, pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))] #[cfg(any(stm32h5, stm32h7))]
pub pll2_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>, pub pll2_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))] #[cfg(any(stm32h5, stm32h7))]
pub pll2_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_r: Option<Hertz>, pub pll2_r: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))] #[cfg(any(stm32h5, stm32h7))]
pub pll3_p: Option<Hertz>, pub pll3_p: Option<Hertz>,

6
embassy-stm32/src/sdmmc/mod.rs
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@ -1457,7 +1457,7 @@ cfg_if::cfg_if! {
macro_rules! kernel_clk { macro_rules! kernel_clk {
($inst:ident) => { ($inst:ident) => {
critical_section::with(|_| unsafe { critical_section::with(|_| unsafe {
crate::rcc::get_freqs().pll48 crate::rcc::get_freqs().pll1_q
}).expect("PLL48 is required for SDIO") }).expect("PLL48 is required for SDIO")
} }
} }
@ -1469,7 +1469,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK { if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
crate::rcc::get_freqs().sys crate::rcc::get_freqs().sys
} else { } else {
crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC") crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
} }
}) })
}; };
@ -1479,7 +1479,7 @@ cfg_if::cfg_if! {
if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK { if sdmmcsel == crate::pac::rcc::vals::Sdmmcsel::SYSCLK {
crate::rcc::get_freqs().sys crate::rcc::get_freqs().sys
} else { } else {
crate::rcc::get_freqs().pll48.expect("PLL48 is required for SDMMC") crate::rcc::get_freqs().pll1_q.expect("PLL48 is required for SDMMC")
} }
}) })
}; };