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STM32: Remove vestigal build.rs cfgs, add new flashsize_X and package_X cfgs, use in F3 RCC

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Adam Greig 2023-11-19 03:06:30 +00:00 committed by Dario Nieuwenhuis
parent f5c9e3baa6
commit 2218d30c80
2 changed files with 5 additions and 18 deletions
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18
embassy-stm32/build.rs
View File

@ -65,7 +65,6 @@ fn main() {
match r.kind { match r.kind {
// Generate singletons per pin, not per port // Generate singletons per pin, not per port
"gpio" => { "gpio" => {
println!("{}", p.name);
let port_letter = p.name.strip_prefix("GPIO").unwrap(); let port_letter = p.name.strip_prefix("GPIO").unwrap();
for pin_num in 0..16 { for pin_num in 0..16 {
singletons.push(format!("P{}{}", port_letter, pin_num)); singletons.push(format!("P{}{}", port_letter, pin_num));
@ -1352,15 +1351,6 @@ fn main() {
if let Some(core) = core_name { if let Some(core) = core_name {
println!("cargo:rustc-cfg={}_{}", &chip_name[..chip_name.len() - 2], core); println!("cargo:rustc-cfg={}_{}", &chip_name[..chip_name.len() - 2], core);
} else {
println!("cargo:rustc-cfg={}", &chip_name[..chip_name.len() - 2]);
}
// ========
// stm32f3 wildcard features used in RCC
if chip_name.starts_with("stm32f3") {
println!("cargo:rustc-cfg={}x{}", &chip_name[..9], &chip_name[10..11]);
} }
// ======= // =======
@ -1375,17 +1365,17 @@ fn main() {
if &chip_name[..8] == "stm32wba" { if &chip_name[..8] == "stm32wba" {
println!("cargo:rustc-cfg={}", &chip_name[..8]); // stm32wba println!("cargo:rustc-cfg={}", &chip_name[..8]); // stm32wba
println!("cargo:rustc-cfg={}", &chip_name[..10]); // stm32wba52 println!("cargo:rustc-cfg={}", &chip_name[..10]); // stm32wba52
println!("cargo:rustc-cfg=package_{}", &chip_name[10..11]);
println!("cargo:rustc-cfg=flashsize_{}", &chip_name[11..12]);
} else { } else {
println!("cargo:rustc-cfg={}", &chip_name[..7]); // stm32f4 println!("cargo:rustc-cfg={}", &chip_name[..7]); // stm32f4
println!("cargo:rustc-cfg={}", &chip_name[..9]); // stm32f429 println!("cargo:rustc-cfg={}", &chip_name[..9]); // stm32f429
println!("cargo:rustc-cfg={}x", &chip_name[..8]); // stm32f42x println!("cargo:rustc-cfg={}x", &chip_name[..8]); // stm32f42x
println!("cargo:rustc-cfg={}x{}", &chip_name[..7], &chip_name[8..9]); // stm32f4x9 println!("cargo:rustc-cfg={}x{}", &chip_name[..7], &chip_name[8..9]); // stm32f4x9
println!("cargo:rustc-cfg=package_{}", &chip_name[9..10]);
println!("cargo:rustc-cfg=flashsize_{}", &chip_name[10..11]);
} }
// Handle time-driver-XXXX features.
if env::var("CARGO_FEATURE_TIME_DRIVER_ANY").is_ok() {}
println!("cargo:rustc-cfg={}", &chip_name[..chip_name.len() - 2]);
println!("cargo:rerun-if-changed=build.rs"); println!("cargo:rerun-if-changed=build.rs");
} }

5
embassy-stm32/src/rcc/f3.rs
View File

@ -346,10 +346,7 @@ fn calc_pll(config: &Config, Hertz(sysclk): Hertz) -> (Hertz, PllConfig) {
None => { None => {
cfg_if::cfg_if! { cfg_if::cfg_if! {
// For some chips PREDIV is always two, and cannot be changed // For some chips PREDIV is always two, and cannot be changed
if #[cfg(any( if #[cfg(any(flashsize_d, flashsize_e))] {
stm32f302xd, stm32f302xe, stm32f303xd,
stm32f303xe, stm32f398xe
))] {
let (multiplier, divisor) = get_mul_div(sysclk, HSI_FREQ.0); let (multiplier, divisor) = get_mul_div(sysclk, HSI_FREQ.0);
( (
Hertz((HSI_FREQ.0 / divisor) * multiplier), Hertz((HSI_FREQ.0 / divisor) * multiplier),