stm32/rcc: fix pll enum naming on f4, f7.

2023-11-13 01:53:27 +01:00
parent f00e97a5f1
commit 2376b3bdfa
10 changed files with 21 additions and 21 deletions
--- a/examples/stm32f4/src/bin/usb_ethernet.rs
+++ b/examples/stm32f4/src/bin/usb_ethernet.rs
@ -56,8 +56,8 @@ async fn main(spawner: Spawner) {
        config.rcc.pll = Some(Pll {
            prediv: PllPreDiv::DIV4,
            mul: PllMul::MUL168,
-            divp: Some(Pllp::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
-            divq: Some(Pllq::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
+            divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 168 / 2 = 168Mhz.
+            divq: Some(PllQDiv::DIV7), // 8mhz / 4 * 168 / 7 = 48Mhz.
            divr: None,
        });
        config.rcc.ahb_pre = AHBPrescaler::DIV1;