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stm32/rcc: fix pll enum naming on f4, f7.

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This commit is contained in:
Dario Nieuwenhuis
2023-11-13 01:53:27 +01:00
parent f00e97a5f1
commit 2376b3bdfa
10 changed files with 21 additions and 21 deletions
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4
tests/stm32/src/common.rs
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@ -271,7 +271,7 @@ pub fn config() -> Config {
config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL180,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 180 / 2 = 180Mhz.
divq: None,
divr: None,
});
@ -292,7 +292,7 @@ pub fn config() -> Config {
config.rcc.pll = Some(Pll {
prediv: PllPreDiv::DIV4,
mul: PllMul::MUL216,
divp: Some(Pllp::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
divp: Some(PllPDiv::DIV2), // 8mhz / 4 * 216 / 2 = 216Mhz.
divq: None,
divr: None,
});