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Adjust example for RCC and DMA.

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This commit is contained in:
Bob McWhirter
2021-06-29 11:00:23 -04:00
parent c53ab325c1
commit 24f18819c8
2 changed files with 5 additions and 5 deletions
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4
examples/stm32f4/src/bin/usart_dma.rs
View File

@@ -23,14 +23,14 @@ async fn main_task() {
let mut p = embassy_stm32::init(Default::default());
let config = Config::default();
let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config, 16_000_000);
let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config);
for n in 0u32.. {
let mut s: String<128> = String::new();
core::write!(&mut s, "Hello DMA World {}!\r\n", n).unwrap();
usart
.write_dma(&mut p.DMA1_CH3, s.as_bytes())
.write_dma(&mut p.DMA1_3, s.as_bytes())
.await
.unwrap();
info!("wrote DMA");

6
stm32-metapac/gen/src/lib.rs
View File

@@ -431,13 +431,13 @@ pub fn gen(options: Options) {
]);
}
(None, Some(_)) => {
println!("Unable to find enable register for {}", name)
panic!("Unable to find enable register for {}", name)
}
(Some(_), None) => {
println!("Unable to find reset register for {}", name)
panic!("Unable to find reset register for {}", name)
}
(None, None) => {
println!("Unable to find enable and reset register for {}", name)
panic!("Unable to find enable and reset register for {}", name)
}
}
}