nrf/uarte: update BufferedUarte to new APi
This commit is contained in:
Dario Nieuwenhuis
parent
00e5f30352
commit
3a18373828
@ -7,54 +7,49 @@
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#[path = "../example_common.rs"]
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mod example_common;
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use core::mem;
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use embassy_nrf::gpio::NoPin;
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use example_common::*;
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use cortex_m_rt::entry;
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use defmt::panic;
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use futures::pin_mut;
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use nrf52840_hal as hal;
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use nrf52840_hal::gpio;
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use nrf52840_hal::clocks;
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use embassy::executor::{task, Executor};
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use embassy::io::{AsyncBufReadExt, AsyncWriteExt};
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use embassy::util::Forever;
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use embassy_nrf::buffered_uarte;
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use embassy_nrf::interrupt;
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static mut TX_BUFFER: [u8; 4096] = [0; 4096];
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static mut RX_BUFFER: [u8; 4096] = [0; 4096];
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use embassy::util::{Forever, Steal};
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use embassy_nrf::{buffered_uarte::BufferedUarte, interrupt, peripherals, rtc, uarte, Peripherals};
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#[task]
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async fn run() {
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let p = unwrap!(embassy_nrf::pac::Peripherals::take());
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let p = unsafe { Peripherals::steal() };
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let port0 = gpio::p0::Parts::new(p.P0);
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let mut config = uarte::Config::default();
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config.parity = uarte::Parity::EXCLUDED;
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config.baudrate = uarte::Baudrate::BAUD115200;
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let pins = buffered_uarte::Pins {
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rxd: port0.p0_08.into_floating_input().degrade(),
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txd: port0
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.p0_06
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.into_push_pull_output(gpio::Level::Low)
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.degrade(),
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cts: None,
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rts: None,
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};
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let ppi = hal::ppi::Parts::new(p.PPI);
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let mut tx_buffer = [0u8; 4096];
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let mut rx_buffer = [0u8; 4096];
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let irq = interrupt::take!(UARTE0_UART0);
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let u = buffered_uarte::BufferedUarte::new(
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p.UARTE0,
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p.TIMER0,
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ppi.ppi0,
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ppi.ppi1,
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irq,
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unsafe { &mut RX_BUFFER },
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unsafe { &mut TX_BUFFER },
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pins,
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buffered_uarte::Parity::EXCLUDED,
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buffered_uarte::Baudrate::BAUD115200,
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);
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let u = unsafe {
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BufferedUarte::new(
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p.UARTE0,
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p.TIMER0,
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p.PPI_CH0,
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p.PPI_CH1,
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irq,
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p.P0_08,
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p.P0_06,
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NoPin,
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NoPin,
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config,
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&mut rx_buffer,
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&mut tx_buffer,
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)
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};
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pin_mut!(u);
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info!("uarte initialized!");
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@ -80,13 +75,30 @@ async fn run() {
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}
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}
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static RTC: Forever<rtc::RTC<peripherals::RTC1>> = Forever::new();
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static ALARM: Forever<rtc::Alarm<peripherals::RTC1>> = Forever::new();
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static EXECUTOR: Forever<Executor> = Forever::new();
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#[entry]
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fn main() -> ! {
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info!("Hello World!");
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let p = unwrap!(embassy_nrf::Peripherals::take());
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clocks::Clocks::new(unsafe { mem::transmute(()) })
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.enable_ext_hfosc()
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.set_lfclk_src_external(clocks::LfOscConfiguration::NoExternalNoBypass)
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.start_lfclk();
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let rtc = RTC.put(rtc::RTC::new(p.RTC1, interrupt::take!(RTC1)));
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rtc.start();
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unsafe { embassy::time::set_clock(rtc) };
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let alarm = ALARM.put(rtc.alarm0());
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let executor = EXECUTOR.put(Executor::new());
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executor.set_alarm(alarm);
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executor.run(|spawner| {
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unwrap!(spawner.spawn(run()));
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});
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@ -11,11 +11,11 @@ defmt-info = [ ]
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defmt-warn = [ ]
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defmt-error = [ ]
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52810 = ["nrf52810-pac", "nrf52810-hal"]
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52811 = ["nrf52811-pac"] #, "nrf52811-hal"]
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52832 = ["nrf52832-pac", "nrf52832-hal"]
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52833 = ["nrf52833-pac", "nrf52833-hal"]
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52840 = ["nrf52840-pac", "nrf52840-hal"]
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52810 = ["nrf52810-pac"]
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52811 = ["nrf52811-pac"]
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52832 = ["nrf52832-pac"]
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52833 = ["nrf52833-pac"]
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52840 = ["nrf52840-pac"]
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[dependencies]
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@ -36,9 +36,3 @@ nrf52811-pac = { version = "0.9.1", optional = true }
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nrf52832-pac = { version = "0.9.0", optional = true }
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nrf52833-pac = { version = "0.9.0", optional = true }
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nrf52840-pac = { version = "0.9.0", optional = true }
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nrf52810-hal = { version = "0.12.1", optional = true }
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#nrf52811-hal = { version = "0.12.1", optional = true } # doesn't exist yet
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nrf52832-hal = { version = "0.12.1", optional = true }
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nrf52833-hal = { version = "0.12.1", optional = true }
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nrf52840-hal = { version = "0.12.1", optional = true }
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@ -1,30 +1,24 @@
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//! HAL interface to the UARTE peripheral
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//!
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//! See product specification:
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//!
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//! - nrf52832: Section 35
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//! - nrf52840: Section 6.34
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use core::cmp::min;
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use core::mem;
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use core::ops::Deref;
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use core::pin::Pin;
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use core::sync::atomic::{compiler_fence, Ordering};
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use core::task::{Context, Poll};
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use embassy::interrupt::InterruptExt;
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use embassy::io::{AsyncBufRead, AsyncWrite, Result};
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use embassy::util::WakerRegistration;
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use embassy_extras::low_power_wait_until;
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use embassy::util::{PeripheralBorrow, WakerRegistration};
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use embassy_extras::peripheral::{PeripheralMutex, PeripheralState};
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use embassy_extras::ring_buffer::RingBuffer;
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use embedded_hal::digital::v2::OutputPin;
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use embassy_extras::{low_power_wait_until, unborrow};
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use crate::fmt::*;
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use crate::hal::ppi::ConfigurablePpi;
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use crate::interrupt::{self, Interrupt};
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use crate::fmt::{panic, *};
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use crate::gpio::sealed::Pin as _;
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use crate::gpio::{OptionalPin as GpioOptionalPin, Pin as GpioPin};
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use crate::pac;
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use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
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use crate::timer::Instance as TimerInstance;
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use crate::uarte::{Config, Instance as UarteInstance};
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// Re-export SVD variants to allow user to directly set values
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pub use crate::hal::uarte::Pins;
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pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Parity};
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#[derive(Copy, Clone, Debug, PartialEq)]
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@ -39,17 +33,17 @@ enum TxState {
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Transmitting(usize),
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}
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struct State<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> {
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struct State<'d, U: UarteInstance, T: TimerInstance> {
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uarte: U,
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timer: T,
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ppi_channel_1: P1,
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ppi_channel_2: P2,
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_ppi_ch1: Ppi<'d, AnyConfigurableChannel>,
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_ppi_ch2: Ppi<'d, AnyConfigurableChannel>,
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rx: RingBuffer<'a>,
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rx: RingBuffer<'d>,
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rx_state: RxState,
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rx_waker: WakerRegistration,
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tx: RingBuffer<'a>,
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tx: RingBuffer<'d>,
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tx_state: TxState,
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tx_waker: WakerRegistration,
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}
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@ -62,115 +56,112 @@ struct State<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: Configu
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/// are disabled before using `Uarte`. See product specification:
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/// - nrf52832: Section 15.2
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/// - nrf52840: Section 6.1.2
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pub struct BufferedUarte<
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'a,
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U: Instance,
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T: TimerInstance,
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P1: ConfigurablePpi,
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P2: ConfigurablePpi,
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> {
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inner: PeripheralMutex<State<'a, U, T, P1, P2>>,
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pub struct BufferedUarte<'d, U: UarteInstance, T: TimerInstance> {
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inner: PeripheralMutex<State<'d, U, T>>,
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}
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impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi>
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BufferedUarte<'a, U, T, P1, P2>
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{
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pub fn new(
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uarte: U,
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timer: T,
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mut ppi_channel_1: P1,
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mut ppi_channel_2: P2,
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irq: U::Interrupt,
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rx_buffer: &'a mut [u8],
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tx_buffer: &'a mut [u8],
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mut pins: Pins,
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parity: Parity,
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baudrate: Baudrate,
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impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
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/// unsafe: may not leak self or futures
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pub unsafe fn new(
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uarte: impl PeripheralBorrow<Target = U> + 'd,
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timer: impl PeripheralBorrow<Target = T> + 'd,
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ppi_ch1: impl PeripheralBorrow<Target = impl ConfigurableChannel> + 'd,
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ppi_ch2: impl PeripheralBorrow<Target = impl ConfigurableChannel> + 'd,
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irq: impl PeripheralBorrow<Target = U::Interrupt> + 'd,
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rxd: impl PeripheralBorrow<Target = impl GpioPin> + 'd,
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txd: impl PeripheralBorrow<Target = impl GpioPin> + 'd,
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cts: impl PeripheralBorrow<Target = impl GpioOptionalPin> + 'd,
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rts: impl PeripheralBorrow<Target = impl GpioOptionalPin> + 'd,
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config: Config,
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rx_buffer: &'d mut [u8],
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tx_buffer: &'d mut [u8],
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) -> Self {
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// Select pins
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uarte.psel.rxd.write(|w| {
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unsafe { w.bits(pins.rxd.psel_bits()) };
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w.connect().connected()
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});
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pins.txd.set_high().unwrap();
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uarte.psel.txd.write(|w| {
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unsafe { w.bits(pins.txd.psel_bits()) };
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w.connect().connected()
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});
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unborrow!(uarte, timer, ppi_ch1, ppi_ch2, irq, rxd, txd, cts, rts);
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// Optional pins
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uarte.psel.cts.write(|w| {
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if let Some(ref pin) = pins.cts {
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unsafe { w.bits(pin.psel_bits()) };
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w.connect().connected()
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} else {
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w.connect().disconnected()
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}
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});
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let r = uarte.regs();
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let rt = timer.regs();
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uarte.psel.rts.write(|w| {
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if let Some(ref pin) = pins.rts {
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unsafe { w.bits(pin.psel_bits()) };
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w.connect().connected()
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} else {
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w.connect().disconnected()
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}
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});
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rxd.conf().write(|w| w.input().connect().drive().h0h1());
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r.psel.rxd.write(|w| unsafe { w.bits(rxd.psel_bits()) });
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// Enable UARTE instance
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uarte.enable.write(|w| w.enable().enabled());
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txd.set_high();
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txd.conf().write(|w| w.dir().output().drive().h0h1());
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r.psel.txd.write(|w| unsafe { w.bits(txd.psel_bits()) });
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// Enable interrupts
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uarte.intenset.write(|w| w.endrx().set().endtx().set());
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if let Some(pin) = rts.pin_mut() {
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pin.set_high();
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pin.conf().write(|w| w.dir().output().drive().h0h1());
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}
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r.psel.cts.write(|w| unsafe { w.bits(cts.psel_bits()) });
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if let Some(pin) = cts.pin_mut() {
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pin.conf().write(|w| w.input().connect().drive().h0h1());
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}
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r.psel.rts.write(|w| unsafe { w.bits(rts.psel_bits()) });
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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r.config.write(|w| w.parity().variant(config.parity));
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// Configure
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let hardware_flow_control = pins.rts.is_some() && pins.cts.is_some();
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uarte
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.config
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.write(|w| w.hwfc().bit(hardware_flow_control).parity().variant(parity));
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let hardware_flow_control = match (rts.pin().is_some(), cts.pin().is_some()) {
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(false, false) => false,
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(true, true) => true,
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_ => panic!("RTS and CTS pins must be either both set or none set."),
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};
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r.config.write(|w| {
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w.hwfc().bit(hardware_flow_control);
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w.parity().variant(config.parity);
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w
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});
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r.baudrate.write(|w| w.baudrate().variant(config.baudrate));
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// Configure frequency
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uarte.baudrate.write(|w| w.baudrate().variant(baudrate));
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// Enable interrupts
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r.intenset.write(|w| w.endrx().set().endtx().set());
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// Disable the irq, let the Registration enable it when everything is set up.
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irq.disable();
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irq.pend();
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// Enable UARTE instance
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r.enable.write(|w| w.enable().enabled());
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// BAUDRATE register values are `baudrate * 2^32 / 16000000`
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// source: https://devzone.nordicsemi.com/f/nordic-q-a/391/uart-baudrate-register-values
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//
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// We want to stop RX if line is idle for 2 bytes worth of time
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// That is 20 bits (each byte is 1 start bit + 8 data bits + 1 stop bit)
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// This gives us the amount of 16M ticks for 20 bits.
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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let timeout = 0x8000_0000 / (config.baudrate as u32 / 40);
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timer.tasks_stop.write(|w| unsafe { w.bits(1) });
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timer.bitmode.write(|w| w.bitmode()._32bit());
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timer.prescaler.write(|w| unsafe { w.prescaler().bits(0) });
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timer.cc[0].write(|w| unsafe { w.bits(timeout) });
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timer.mode.write(|w| w.mode().timer());
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timer.shorts.write(|w| {
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rt.tasks_stop.write(|w| unsafe { w.bits(1) });
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rt.bitmode.write(|w| w.bitmode()._32bit());
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rt.prescaler.write(|w| unsafe { w.prescaler().bits(0) });
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rt.cc[0].write(|w| unsafe { w.bits(timeout) });
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rt.mode.write(|w| w.mode().timer());
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rt.shorts.write(|w| {
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w.compare0_clear().set_bit();
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w.compare0_stop().set_bit();
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w
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});
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ppi_channel_1.set_event_endpoint(&uarte.events_rxdrdy);
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ppi_channel_1.set_task_endpoint(&timer.tasks_clear);
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ppi_channel_1.set_fork_task_endpoint(&timer.tasks_start);
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ppi_channel_1.enable();
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let mut ppi_ch1 = Ppi::new(ppi_ch1.degrade_configurable());
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ppi_ch1.set_event(Event::from_reg(&r.events_rxdrdy));
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ppi_ch1.set_task(Task::from_reg(&rt.tasks_clear));
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ppi_ch1.set_fork_task(Task::from_reg(&rt.tasks_start));
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ppi_ch1.enable();
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ppi_channel_2.set_event_endpoint(&timer.events_compare[0]);
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ppi_channel_2.set_task_endpoint(&uarte.tasks_stoprx);
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ppi_channel_2.enable();
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let mut ppi_ch2 = Ppi::new(ppi_ch2.degrade_configurable());
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ppi_ch2.set_event(Event::from_reg(&rt.events_compare[0]));
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ppi_ch2.set_task(Task::from_reg(&r.tasks_stoprx));
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ppi_ch2.enable();
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BufferedUarte {
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inner: PeripheralMutex::new(
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State {
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uarte,
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timer,
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ppi_channel_1,
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ppi_channel_2,
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_ppi_ch1: ppi_ch1,
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_ppi_ch2: ppi_ch2,
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rx: RingBuffer::new(rx_buffer),
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rx_state: RxState::Idle,
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@ -187,25 +178,23 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
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pub fn set_baudrate(self: Pin<&mut Self>, baudrate: Baudrate) {
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self.inner().with(|state, _irq| {
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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state.timer.cc[0].write(|w| unsafe { w.bits(timeout) });
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state.timer.tasks_clear.write(|w| unsafe { w.bits(1) });
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let r = state.uarte.regs();
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let rt = state.timer.regs();
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state
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.uarte
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.baudrate
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.write(|w| w.baudrate().variant(baudrate));
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let timeout = 0x8000_0000 / (baudrate as u32 / 40);
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rt.cc[0].write(|w| unsafe { w.bits(timeout) });
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rt.tasks_clear.write(|w| unsafe { w.bits(1) });
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r.baudrate.write(|w| w.baudrate().variant(baudrate));
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});
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}
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fn inner(self: Pin<&mut Self>) -> Pin<&mut PeripheralMutex<State<'a, U, T, P1, P2>>> {
|
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fn inner(self: Pin<&mut Self>) -> Pin<&mut PeripheralMutex<State<'d, U, T>>> {
|
||||
unsafe { Pin::new_unchecked(&mut self.get_unchecked_mut().inner) }
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> AsyncBufRead
|
||||
for BufferedUarte<'a, U, T, P1, P2>
|
||||
{
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> AsyncBufRead for BufferedUarte<'d, U, T> {
|
||||
fn poll_fill_buf(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Result<&[u8]>> {
|
||||
let mut inner = self.inner();
|
||||
inner.as_mut().register_interrupt();
|
||||
@ -242,9 +231,7 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> AsyncWrite
|
||||
for BufferedUarte<'a, U, T, P1, P2>
|
||||
{
|
||||
impl<'d, U: UarteInstance, T: TimerInstance> AsyncWrite for BufferedUarte<'d, U, T> {
|
||||
fn poll_write(self: Pin<&mut Self>, cx: &mut Context<'_>, buf: &[u8]) -> Poll<Result<usize>> {
|
||||
let mut inner = self.inner();
|
||||
inner.as_mut().register_interrupt();
|
||||
@ -276,32 +263,36 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> Drop
|
||||
for State<'a, U, T, P1, P2>
|
||||
{
|
||||
impl<'a, U: UarteInstance, T: TimerInstance> Drop for State<'a, U, T> {
|
||||
fn drop(&mut self) {
|
||||
self.timer.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
let r = self.uarte.regs();
|
||||
let rt = self.timer.regs();
|
||||
|
||||
// TODO this probably deadlocks. do like Uarte instead.
|
||||
|
||||
rt.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
if let RxState::Receiving = self.rx_state {
|
||||
self.uarte.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
||||
r.tasks_stoprx.write(|w| unsafe { w.bits(1) });
|
||||
}
|
||||
if let TxState::Transmitting(_) = self.tx_state {
|
||||
self.uarte.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
||||
r.tasks_stoptx.write(|w| unsafe { w.bits(1) });
|
||||
}
|
||||
if let RxState::Receiving = self.rx_state {
|
||||
low_power_wait_until(|| self.uarte.events_endrx.read().bits() == 1);
|
||||
low_power_wait_until(|| r.events_endrx.read().bits() == 1);
|
||||
}
|
||||
if let TxState::Transmitting(_) = self.tx_state {
|
||||
low_power_wait_until(|| self.uarte.events_endtx.read().bits() == 1);
|
||||
low_power_wait_until(|| r.events_endtx.read().bits() == 1);
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi> PeripheralState
|
||||
for State<'a, U, T, P1, P2>
|
||||
{
|
||||
impl<'a, U: UarteInstance, T: TimerInstance> PeripheralState for State<'a, U, T> {
|
||||
type Interrupt = U::Interrupt;
|
||||
fn on_interrupt(&mut self) {
|
||||
trace!("irq: start");
|
||||
let r = self.uarte.regs();
|
||||
let rt = self.timer.regs();
|
||||
|
||||
loop {
|
||||
match self.rx_state {
|
||||
RxState::Idle => {
|
||||
@ -313,11 +304,11 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
self.rx_state = RxState::Receiving;
|
||||
|
||||
// Set up the DMA read
|
||||
self.uarte.rxd.ptr.write(|w|
|
||||
r.rxd.ptr.write(|w|
|
||||
// The PTR field is a full 32 bits wide and accepts the full range
|
||||
// of values.
|
||||
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
|
||||
self.uarte.rxd.maxcnt.write(|w|
|
||||
r.rxd.maxcnt.write(|w|
|
||||
// We're giving it the length of the buffer, so no danger of
|
||||
// accessing invalid memory. We have verified that the length of the
|
||||
// buffer fits in an `u8`, so the cast to `u8` is also fine.
|
||||
@ -328,7 +319,7 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
trace!(" irq_rx: buf {:?} {:?}", buf.as_ptr() as u32, buf.len());
|
||||
|
||||
// Start UARTE Receive transaction
|
||||
self.uarte.tasks_startrx.write(|w|
|
||||
r.tasks_startrx.write(|w|
|
||||
// `1` is a valid value to write to task registers.
|
||||
unsafe { w.bits(1) });
|
||||
}
|
||||
@ -336,14 +327,14 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
}
|
||||
RxState::Receiving => {
|
||||
trace!(" irq_rx: in state receiving");
|
||||
if self.uarte.events_endrx.read().bits() != 0 {
|
||||
self.timer.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
if r.events_endrx.read().bits() != 0 {
|
||||
rt.tasks_stop.write(|w| unsafe { w.bits(1) });
|
||||
|
||||
let n: usize = self.uarte.rxd.amount.read().amount().bits() as usize;
|
||||
let n: usize = r.rxd.amount.read().amount().bits() as usize;
|
||||
trace!(" irq_rx: endrx {:?}", n);
|
||||
self.rx.push(n);
|
||||
|
||||
self.uarte.events_endrx.reset();
|
||||
r.events_endrx.reset();
|
||||
|
||||
self.rx_waker.wake();
|
||||
self.rx_state = RxState::Idle;
|
||||
@ -364,11 +355,11 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
self.tx_state = TxState::Transmitting(buf.len());
|
||||
|
||||
// Set up the DMA write
|
||||
self.uarte.txd.ptr.write(|w|
|
||||
r.txd.ptr.write(|w|
|
||||
// The PTR field is a full 32 bits wide and accepts the full range
|
||||
// of values.
|
||||
unsafe { w.ptr().bits(buf.as_ptr() as u32) });
|
||||
self.uarte.txd.maxcnt.write(|w|
|
||||
r.txd.maxcnt.write(|w|
|
||||
// We're giving it the length of the buffer, so no danger of
|
||||
// accessing invalid memory. We have verified that the length of the
|
||||
// buffer fits in an `u8`, so the cast to `u8` is also fine.
|
||||
@ -378,7 +369,7 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
unsafe { w.maxcnt().bits(buf.len() as _) });
|
||||
|
||||
// Start UARTE Transmit transaction
|
||||
self.uarte.tasks_starttx.write(|w|
|
||||
r.tasks_starttx.write(|w|
|
||||
// `1` is a valid value to write to task registers.
|
||||
unsafe { w.bits(1) });
|
||||
}
|
||||
@ -386,8 +377,8 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
}
|
||||
TxState::Transmitting(n) => {
|
||||
trace!(" irq_tx: in state Transmitting");
|
||||
if self.uarte.events_endtx.read().bits() != 0 {
|
||||
self.uarte.events_endtx.reset();
|
||||
if r.events_endtx.read().bits() != 0 {
|
||||
r.events_endtx.reset();
|
||||
|
||||
trace!(" irq_tx: endtx {:?}", n);
|
||||
self.tx.pop(n);
|
||||
@ -402,37 +393,3 @@ impl<'a, U: Instance, T: TimerInstance, P1: ConfigurablePpi, P2: ConfigurablePpi
|
||||
trace!("irq: end");
|
||||
}
|
||||
}
|
||||
|
||||
mod sealed {
|
||||
pub trait Instance {}
|
||||
|
||||
impl Instance for crate::pac::UARTE0 {}
|
||||
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
|
||||
impl Instance for crate::pac::UARTE1 {}
|
||||
|
||||
pub trait TimerInstance {}
|
||||
impl TimerInstance for crate::pac::TIMER0 {}
|
||||
impl TimerInstance for crate::pac::TIMER1 {}
|
||||
impl TimerInstance for crate::pac::TIMER2 {}
|
||||
}
|
||||
|
||||
pub trait Instance: Deref<Target = pac::uarte0::RegisterBlock> + sealed::Instance {
|
||||
type Interrupt: Interrupt;
|
||||
}
|
||||
|
||||
impl Instance for pac::UARTE0 {
|
||||
type Interrupt = interrupt::UARTE0_UART0;
|
||||
}
|
||||
|
||||
#[cfg(any(feature = "52833", feature = "52840", feature = "9160"))]
|
||||
impl Instance for pac::UARTE1 {
|
||||
type Interrupt = interrupt::UARTE1;
|
||||
}
|
||||
|
||||
pub trait TimerInstance:
|
||||
Deref<Target = pac::timer0::RegisterBlock> + sealed::TimerInstance
|
||||
{
|
||||
}
|
||||
impl TimerInstance for crate::pac::TIMER0 {}
|
||||
impl TimerInstance for crate::pac::TIMER1 {}
|
||||
impl TimerInstance for crate::pac::TIMER2 {}
|
||||
|
||||
@ -40,17 +40,6 @@ pub use nrf52833_pac as pac;
|
||||
#[cfg(feature = "52840")]
|
||||
pub use nrf52840_pac as pac;
|
||||
|
||||
#[cfg(feature = "52810")]
|
||||
pub use nrf52810_hal as hal;
|
||||
#[cfg(feature = "52811")]
|
||||
pub use nrf52811_hal as hal;
|
||||
#[cfg(feature = "52832")]
|
||||
pub use nrf52832_hal as hal;
|
||||
#[cfg(feature = "52833")]
|
||||
pub use nrf52833_hal as hal;
|
||||
#[cfg(feature = "52840")]
|
||||
pub use nrf52840_hal as hal;
|
||||
|
||||
/// Length of Nordic EasyDMA differs for MCUs
|
||||
#[cfg(any(
|
||||
feature = "52810",
|
||||
|
||||
Loading…
Reference in New Issue
Block a user