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cortex-m: remove owned interrupts.

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This commit is contained in:
Dario Nieuwenhuis
2023-06-01 02:22:46 +02:00
parent 2a435e53b7
commit 404aa29289
54 changed files with 239 additions and 439 deletions
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18
embassy-stm32/src/usart/buffered.rs
View File

@ -216,8 +216,8 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
});
}
unsafe { T::Interrupt::steal() }.unpend();
unsafe { T::Interrupt::steal() }.enable();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
Self {
rx: BufferedUartRx { phantom: PhantomData },
@ -245,7 +245,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
rx_reader.pop_done(len);
if do_pend {
unsafe { T::Interrupt::steal().pend() };
T::Interrupt::pend();
}
return Poll::Ready(Ok(len));
@ -271,7 +271,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
rx_reader.pop_done(len);
if do_pend {
unsafe { T::Interrupt::steal().pend() };
T::Interrupt::pend();
}
return Ok(len);
@ -301,7 +301,7 @@ impl<'d, T: BasicInstance> BufferedUartRx<'d, T> {
let full = state.rx_buf.is_full();
rx_reader.pop_done(amt);
if full {
unsafe { T::Interrupt::steal().pend() };
T::Interrupt::pend();
}
}
}
@ -324,7 +324,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
tx_writer.push_done(n);
if empty {
unsafe { T::Interrupt::steal() }.pend();
T::Interrupt::pend();
}
Poll::Ready(Ok(n))
@ -358,7 +358,7 @@ impl<'d, T: BasicInstance> BufferedUartTx<'d, T> {
tx_writer.push_done(n);
if empty {
unsafe { T::Interrupt::steal() }.pend();
T::Interrupt::pend();
}
return Ok(n);
@ -385,7 +385,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartRx<'d, T> {
// TX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler
if state.tx_buf.len() == 0 {
T::Interrupt::steal().disable();
T::Interrupt::disable();
}
}
}
@ -400,7 +400,7 @@ impl<'d, T: BasicInstance> Drop for BufferedUartTx<'d, T> {
// RX is inactive if the the buffer is not available.
// We can now unregister the interrupt handler
if state.rx_buf.len() == 0 {
T::Interrupt::steal().disable();
T::Interrupt::disable();
}
}
}

10
embassy-stm32/src/usart/mod.rs
View File

@ -5,7 +5,7 @@ use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::{Interrupt, InterruptExt};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use futures::future::{select, Either};
@ -331,8 +331,8 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
configure(r, &config, T::frequency(), T::KIND, true, false);
unsafe { T::Interrupt::steal() }.unpend();
unsafe { T::Interrupt::steal() }.enable();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
// create state once!
let _s = T::state();
@ -732,8 +732,8 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
configure(r, &config, T::frequency(), T::KIND, true, true);
unsafe { T::Interrupt::steal() }.unpend();
unsafe { T::Interrupt::steal() }.enable();
T::Interrupt::unpend();
unsafe { T::Interrupt::enable() };
// create state once!
let _s = T::state();