fix transfer mutability
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xoviat
parent
53c2829eb1
commit
41db867d9a
@ -33,7 +33,7 @@ use crate::hal::rcc::Clocks;
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use crate::hal::serial::config::{
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Config as SerialConfig, DmaConfig as SerialDmaConfig, Parity, StopBits, WordLength,
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};
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use crate::hal::serial::Serial;
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use crate::hal::serial::{Event as SerialEvent, Serial};
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use crate::hal::time::Bps;
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use crate::interrupt;
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@ -48,9 +48,11 @@ use embedded_hal::digital::v2::OutputPin;
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/// Interface to the UARTE peripheral
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pub struct Uarte {
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instance: Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>,
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usart: USART1,
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dma: DMA2,
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// tx_transfer: Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, &mut [u8; 20]>,
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// rx_transfer: Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, &mut [u8; 20]>,
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tx_stream: Option<Stream7<DMA2>>,
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rx_stream: Option<Stream2<DMA2>>,
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usart: Option<USART1>,
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}
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struct State {
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@ -63,15 +65,16 @@ static STATE: State = State {
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rx_done: Signal::new(),
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};
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pub struct Pins {
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pub rxd: PA10<Alternate<AF7>>,
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pub txd: PA9<Alternate<AF7>>,
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pub dma: DMA2,
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pub usart: USART1,
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}
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impl Uarte {
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pub fn new(mut pins: Pins, parity: Parity, baudrate: Bps, clocks: Clocks) -> Self {
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pub fn new(
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rxd: PA10<Alternate<AF7>>,
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txd: PA9<Alternate<AF7>>,
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dma: DMA2,
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usart: USART1,
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parity: Parity,
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baudrate: Bps,
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clocks: Clocks,
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) -> Self {
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// // Enable interrupts
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// uarte.events_endtx.reset();
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// uarte.events_endrx.reset();
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@ -83,9 +86,9 @@ impl Uarte {
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// interrupt::enable(interrupt::UARTE0_UART0);
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// Serial<USART1, (PA9<Alternate<AF7>>, PA10<Alternate<AF7>>)>
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let mut serial = Serial::usart1(
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pins.usart,
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(pins.txd, pins.rxd),
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let serial = Serial::usart1(
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usart,
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(txd, rxd),
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SerialConfig {
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baudrate: baudrate,
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wordlength: WordLength::DataBits8,
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@ -97,12 +100,24 @@ impl Uarte {
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)
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.unwrap();
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// let is_set = dma.hifcr.read().tcif7.bit_is_set();
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let (usart, _) = serial.release();
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/*
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Note: for our application, it would be approrpiate to listen for idle events,
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and to establish a method to capture data until idle.
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*/
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// serial.listen(SerialEvent::Idle);
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// tx_transfer.start(|usart| {
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// // usart.cr2.modify(|_, w| w.swstart().start());
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// });
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let streams = StreamsTuple::new(dma);
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Uarte {
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instance: serial,
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dma: pins.dma,
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usart: pins.usart,
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tx_stream: Some(streams.7),
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rx_stream: Some(streams.2),
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usart: Some(usart),
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}
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}
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@ -115,10 +130,21 @@ impl Uarte {
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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let tx_stream = self.tx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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SendFuture {
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uarte: self,
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buf: tx_buffer,
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transfer: None,
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tx_transfer: Transfer::init(
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tx_stream,
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usart,
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tx_buffer,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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),
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}
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}
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@ -136,10 +162,22 @@ impl Uarte {
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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let rx_stream = self.rx_stream.take().unwrap();
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let usart = self.usart.take().unwrap();
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ReceiveFuture {
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uarte: self,
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buf: rx_buffer,
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transfer: None,
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rx_transfer: Transfer::init(
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rx_stream,
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usart,
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rx_buffer,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.half_transfer_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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),
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}
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}
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}
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@ -147,17 +185,14 @@ impl Uarte {
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/// Future for the [`LowPowerUarte::send()`] method.
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pub struct SendFuture<'a, B: WriteBuffer<Word = u8> + 'static> {
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uarte: &'a Uarte,
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transfer: Option<&'a Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, B>>,
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buf: B,
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tx_transfer: Transfer<Stream7<DMA2>, Channel4, USART1, MemoryToPeripheral, B>,
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}
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impl<'a, B> Drop for SendFuture<'a, B>
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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fn drop(self: &mut Self) {
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drop(self.transfer);
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}
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fn drop(self: &mut Self) {}
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}
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impl<'a, B> Future for SendFuture<'a, B>
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@ -167,20 +202,10 @@ where
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type Output = ();
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<()> {
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if !self.transfer.is_none() && self.transfer.unwrap().is_done() {
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if self.tx_transfer.is_done() {
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Poll::Ready(())
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} else {
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self.transfer = Some(&mut Transfer::init(
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StreamsTuple::new(self.uarte.dma).7,
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self.uarte.usart,
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self.buf,
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// Some(second_buffer),
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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));
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// self.0.as_mut().tx_transfer.start(|usart| {});
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waker_interrupt!(DMA2_STREAM7, cx.waker().clone());
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Poll::Pending
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@ -191,17 +216,14 @@ where
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/// Future for the [`Uarte::receive()`] method.
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pub struct ReceiveFuture<'a, B: WriteBuffer<Word = u8> + 'static> {
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uarte: &'a Uarte,
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transfer: Option<&'a Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, B>>,
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buf: B,
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rx_transfer: Transfer<Stream2<DMA2>, Channel4, USART1, PeripheralToMemory, B>,
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}
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impl<'a, B> Drop for ReceiveFuture<'a, B>
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where
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B: WriteBuffer<Word = u8> + 'static,
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{
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fn drop(self: &mut Self) {
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drop(self.transfer);
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}
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fn drop(self: &mut Self) {}
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}
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impl<'a, B> Future for ReceiveFuture<'a, B>
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@ -211,23 +233,23 @@ where
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type Output = B;
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fn poll(self: core::pin::Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<B> {
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if !self.transfer.is_none() && self.transfer.unwrap().is_done() {
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Poll::Ready(self.buf.take());
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} else {
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self.transfer = Some(&mut Transfer::init(
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StreamsTuple::new(self.uarte.dma).2,
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self.uarte.usart,
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self.buf,
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None,
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DmaConfig::default()
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.transfer_complete_interrupt(true)
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.half_transfer_interrupt(true)
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.memory_increment(true)
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.double_buffer(false),
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));
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// if !self.transfer.is_none() && self.transfer.unwrap().is_done() {
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// Poll::Ready(self.buf.take());
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// } else {
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// self.transfer = Some(&mut Transfer::init(
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// StreamsTuple::new(self.uarte.dma).2,
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// self.uarte.usart,
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// self.buf,
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// None,
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// DmaConfig::default()
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// .transfer_complete_interrupt(true)
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// .half_transfer_interrupt(true)
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// .memory_increment(true)
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// .double_buffer(false),
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// ));
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waker_interrupt!(DMA2_STREAM2, cx.waker().clone());
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Poll::Pending
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}
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waker_interrupt!(DMA2_STREAM2, cx.waker().clone());
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Poll::Pending
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// }
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}
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}
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