stm32-metapac: remove all macrotables, deduplicate metadata files.

stm32-metapac/Cargo.toml

@@ -3,6 +3,21 @@ name = "stm32-metapac"
 version = "0.1.0"
 edition = "2018"
 resolver = "2"
+license = "MIT OR Apache-2.0"
+repository = "https://github.com/embassy-rs/embassy"
+description = "Peripheral Access Crate (PAC) for all STM32 chips, including metadata."
+
+# `cargo publish` is unable to figure out which .rs files are needed due to the include! magic.
+include = [
+    "**/*.rs",
+    "**/*.x",
+    "Cargo.toml",
+]
+
+[package.metadata.docs.rs]
+features = ["stm32h755zi-cm7", "pac", "metadata"]
+default-target = "thumbv7em-none-eabihf"
+targets = []
 
 [dependencies]
 cortex-m = "0.7.3"

stm32-metapac/build.rs

@@ -6,7 +6,7 @@ fn parse_chip_core(chip_and_core: &str) -> (String, Option<String>) {
     let mut s = chip_and_core.split('-');
     let chip_name: String = s.next().unwrap().to_string();
     if let Some(c) = s.next() {
-        if c.starts_with("CM") {
+        if c.starts_with("cm") {
             return (chip_name, Some(c.to_ascii_lowercase()));
         }
     }
@@ -18,36 +18,45 @@ fn main() {
     let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
     let data_dir = PathBuf::from("../stm32-data/data");
 
-    println!("cwd: {:?}", env::current_dir());
-
     let chip_core_name = env::vars_os()
         .map(|(a, _)| a.to_string_lossy().to_string())
         .find(|x| x.starts_with("CARGO_FEATURE_STM32"))
         .expect("No stm32xx Cargo feature enabled")
         .strip_prefix("CARGO_FEATURE_")
         .unwrap()
-        .to_ascii_uppercase()
+        .to_ascii_lowercase()
         .replace('_', "-");
 
     let (chip_name, _) = parse_chip_core(&chip_core_name);
 
-    gen(Options {
+    let opts = Options {
         out_dir: out_dir.clone(),
         data_dir: data_dir.clone(),
-        chips: vec![chip_name],
-    });
+        chips: vec![chip_name.to_ascii_uppercase()],
+    };
+    Gen::new(opts).gen();
 
     println!(
         "cargo:rustc-link-search={}/src/chips/{}",
         out_dir.display(),
-        chip_core_name.to_ascii_lowercase()
+        chip_core_name,
     );
 
     #[cfg(feature = "memory-x")]
     println!(
         "cargo:rustc-link-search={}/src/chips/{}/memory_x/",
         out_dir.display(),
-        chip_core_name.to_ascii_lowercase()
+        chip_core_name
+    );
+    println!(
+        "cargo:rustc-env=STM32_METAPAC_PAC_PATH={}/src/chips/{}/pac.rs",
+        out_dir.display(),
+        chip_core_name
+    );
+    println!(
+        "cargo:rustc-env=STM32_METAPAC_METADATA_PATH={}/src/chips/{}/metadata.rs",
+        out_dir.display(),
+        chip_core_name
     );
 
     println!("cargo:rerun-if-changed=build.rs");

stm32-metapac/build_pregenerated.rs

@@ -0,0 +1,38 @@
+use std::env;
+use std::path::PathBuf;
+
+fn main() {
+    let crate_dir = PathBuf::from(env::var_os("CARGO_MANIFEST_DIR").unwrap());
+
+    let chip_core_name = env::vars_os()
+        .map(|(a, _)| a.to_string_lossy().to_string())
+        .find(|x| x.starts_with("CARGO_FEATURE_STM32"))
+        .expect("No stm32xx Cargo feature enabled")
+        .strip_prefix("CARGO_FEATURE_")
+        .unwrap()
+        .to_ascii_lowercase()
+        .replace('_', "-");
+
+    println!(
+        "cargo:rustc-link-search={}/src/chips/{}",
+        crate_dir.display(),
+        chip_core_name,
+    );
+
+    #[cfg(feature = "memory-x")]
+    println!(
+        "cargo:rustc-link-search={}/src/chips/{}/memory_x/",
+        crate_dir.display(),
+        chip_core_name
+    );
+    println!(
+        "cargo:rustc-env=STM32_METAPAC_PAC_PATH=chips/{}/pac.rs",
+        chip_core_name
+    );
+    println!(
+        "cargo:rustc-env=STM32_METAPAC_METADATA_PATH=chips/{}/metadata.rs",
+        chip_core_name
+    );
+
+    println!("cargo:rerun-if-changed=build.rs");
+}

stm32-metapac/src/common.rs

@@ -0,0 +1,80 @@
+use core::marker::PhantomData;
+
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct RW;
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct R;
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct W;
+
+mod sealed {
+    use super::*;
+    pub trait Access {}
+    impl Access for R {}
+    impl Access for W {}
+    impl Access for RW {}
+}
+
+pub trait Access: sealed::Access + Copy {}
+impl Access for R {}
+impl Access for W {}
+impl Access for RW {}
+
+pub trait Read: Access {}
+impl Read for RW {}
+impl Read for R {}
+
+pub trait Write: Access {}
+impl Write for RW {}
+impl Write for W {}
+
+#[derive(Copy, Clone, PartialEq, Eq)]
+pub struct Reg<T: Copy, A: Access> {
+    ptr: *mut u8,
+    phantom: PhantomData<*mut (T, A)>,
+}
+unsafe impl<T: Copy, A: Access> Send for Reg<T, A> {}
+unsafe impl<T: Copy, A: Access> Sync for Reg<T, A> {}
+
+impl<T: Copy, A: Access> Reg<T, A> {
+    pub fn from_ptr(ptr: *mut u8) -> Self {
+        Self {
+            ptr,
+            phantom: PhantomData,
+        }
+    }
+
+    pub fn ptr(&self) -> *mut T {
+        self.ptr as _
+    }
+}
+
+impl<T: Copy, A: Read> Reg<T, A> {
+    pub unsafe fn read(&self) -> T {
+        (self.ptr as *mut T).read_volatile()
+    }
+}
+
+impl<T: Copy, A: Write> Reg<T, A> {
+    pub unsafe fn write_value(&self, val: T) {
+        (self.ptr as *mut T).write_volatile(val)
+    }
+}
+
+impl<T: Default + Copy, A: Write> Reg<T, A> {
+    pub unsafe fn write<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+        let mut val = Default::default();
+        let res = f(&mut val);
+        self.write_value(val);
+        res
+    }
+}
+
+impl<T: Copy, A: Read + Write> Reg<T, A> {
+    pub unsafe fn modify<R>(&self, f: impl FnOnce(&mut T) -> R) -> R {
+        let mut val = self.read();
+        let res = f(&mut val);
+        self.write_value(val);
+        res
+    }
+}

stm32-metapac/src/lib.rs

@@ -3,5 +3,13 @@
 #![allow(unused)]
 #![allow(non_camel_case_types)]
 
-// GEN CUT HERE
-include!(concat!(env!("OUT_DIR"), "/src/lib_inner.rs"));
+pub mod common;
+
+#[cfg(feature = "pac")]
+include!(env!("STM32_METAPAC_PAC_PATH"));
+
+#[cfg(feature = "metadata")]
+pub mod metadata {
+    include!("metadata.rs");
+    include!(env!("STM32_METAPAC_METADATA_PATH"));
+}

stm32-metapac/src/metadata.rs

@@ -0,0 +1,97 @@
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct Metadata {
+    pub name: &'static str,
+    pub family: &'static str,
+    pub line: &'static str,
+    pub memory: &'static [MemoryRegion],
+    pub peripherals: &'static [Peripheral],
+    pub interrupts: &'static [Interrupt],
+    pub dma_channels: &'static [DmaChannel],
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct MemoryRegion {
+    pub name: &'static str,
+    pub kind: MemoryRegionKind,
+    pub address: u32,
+    pub size: u32,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub enum MemoryRegionKind {
+    Flash,
+    Ram,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct Interrupt {
+    pub name: &'static str,
+    pub number: u32,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct Package {
+    pub name: &'static str,
+    pub package: &'static str,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct Peripheral {
+    pub name: &'static str,
+    pub address: u64,
+    pub registers: Option<PeripheralRegisters>,
+    pub rcc: Option<PeripheralRcc>,
+    pub pins: &'static [PeripheralPin],
+    pub dma_channels: &'static [PeripheralDmaChannel],
+    pub interrupts: &'static [PeripheralInterrupt],
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralRegisters {
+    pub kind: &'static str,
+    pub version: &'static str,
+    pub block: &'static str,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralInterrupt {
+    pub signal: &'static str,
+    pub interrupt: &'static str,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralRcc {
+    pub clock: &'static str,
+    pub enable: Option<PeripheralRccRegister>,
+    pub reset: Option<PeripheralRccRegister>,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralRccRegister {
+    pub register: &'static str,
+    pub field: &'static str,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralPin {
+    pub pin: &'static str,
+    pub signal: &'static str,
+    pub af: Option<u8>,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct DmaChannel {
+    pub name: &'static str,
+    pub dma: &'static str,
+    pub channel: u32,
+    pub dmamux: Option<&'static str>,
+    pub dmamux_channel: Option<u32>,
+}
+
+#[derive(Debug, Eq, PartialEq, Clone)]
+pub struct PeripheralDmaChannel {
+    pub signal: &'static str,
+    pub channel: Option<&'static str>,
+    pub dmamux: Option<&'static str>,
+    pub request: Option<u32>,
+}