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stm32: expand rcc mux to g4 and h7

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This commit is contained in:
xoviat
2023-10-14 23:33:57 -05:00
parent c46e758e2c
commit 4a156df7a1
6 changed files with 72 additions and 74 deletions
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17
embassy-stm32/src/rcc/g4.rs
View File

@ -119,8 +119,8 @@ impl Default for Config {
low_power_run: false,
pll: None,
clock_48mhz_src: None,
adc12_clock_source: Adcsel::NOCLK,
adc345_clock_source: Adcsel::NOCLK,
adc12_clock_source: Adcsel::DISABLE,
adc345_clock_source: Adcsel::DISABLE,
ls: Default::default(),
}
}
@ -326,16 +326,16 @@ pub(crate) unsafe fn init(config: Config) {
RCC.ccipr().modify(|w| w.set_adc345sel(config.adc345_clock_source));
let adc12_ck = match config.adc12_clock_source {
AdcClockSource::NOCLK => None,
AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYSCLK => Some(sys_clk),
AdcClockSource::DISABLE => None,
AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(),
};
let adc345_ck = match config.adc345_clock_source {
AdcClockSource::NOCLK => None,
AdcClockSource::PLLP => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYSCLK => Some(sys_clk),
AdcClockSource::DISABLE => None,
AdcClockSource::PLL1_P => pll_freq.as_ref().unwrap().pll_p,
AdcClockSource::SYS => Some(sys_clk),
_ => unreachable!(),
};
@ -356,6 +356,7 @@ pub(crate) unsafe fn init(config: Config) {
apb2_tim: apb2_tim_freq,
adc: adc12_ck,
adc34: adc345_ck,
pll1_p: None,
rtc,
});
}

33
embassy-stm32/src/rcc/h.rs
View File

@ -446,7 +446,7 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)]
let adc = match config.adc_clock_source {
AdcClockSource::HCLK => Some(hclk),
AdcClockSource::SYSCLK => Some(sys),
AdcClockSource::SYS => Some(sys),
AdcClockSource::PLL2_R => pll2.r,
AdcClockSource::HSE => hse,
AdcClockSource::HSI => hsi,
@ -540,36 +540,34 @@ pub(crate) unsafe fn init(config: Config) {
adc,
rtc,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
hsi: None,
#[cfg(stm32h5)]
hsi48: None,
#[cfg(stm32h5)]
lsi: None,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
csi: None,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
lse: None,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
hse: None,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pll1_q: pll1.q,
#[cfg(stm32h5)]
pll2_q: pll2.q,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pll2_p: pll2.p,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pll2_q: pll2.q,
#[cfg(any(stm32h5, stm32h7))]
pll2_r: pll2.r,
#[cfg(rcc_h5)]
#[cfg(any(rcc_h5, stm32h7))]
pll3_p: pll3.p,
#[cfg(rcc_h5)]
#[cfg(any(rcc_h5, stm32h7))]
pll3_q: pll3.q,
#[cfg(rcc_h5)]
#[cfg(any(rcc_h5, stm32h7))]
pll3_r: pll3.r,
#[cfg(stm32h5)]
pll3_1: None,
#[cfg(rcc_h50)]
pll3_p: None,
@ -580,8 +578,11 @@ pub(crate) unsafe fn init(config: Config) {
#[cfg(stm32h5)]
audioclk: None,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
per: None,
#[cfg(stm32h7)]
rcc_pclk_d3: None,
});
}

47
embassy-stm32/src/rcc/mod.rs
View File

@ -113,6 +113,23 @@ pub struct Clocks {
#[cfg(any(stm32f427, stm32f429, stm32f437, stm32f439, stm32f446, stm32f469, stm32f479))]
pub pllsai: Option<Hertz>,
#[cfg(stm32g4)]
pub pll1_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll1_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll2_r: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_p: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_q: Option<Hertz>,
#[cfg(any(stm32h5, stm32h7))]
pub pll3_r: Option<Hertz>,
#[cfg(any(
rcc_f1,
rcc_f100,
@ -135,41 +152,27 @@ pub struct Clocks {
pub rtc: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pub hsi: Option<Hertz>,
#[cfg(stm32h5)]
pub hsi48: Option<Hertz>,
#[cfg(stm32h5)]
pub lsi: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pub csi: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pub lse: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pub hse: Option<Hertz>,
#[cfg(stm32h5)]
pub pll1_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_p: Option<Hertz>,
#[cfg(stm32h5)]
pub pll2_r: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_p: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_q: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_r: Option<Hertz>,
#[cfg(stm32h5)]
pub pll3_1: Option<Hertz>,
#[cfg(stm32h5)]
pub audioclk: Option<Hertz>,
#[cfg(stm32h5)]
#[cfg(any(stm32h5, stm32h7))]
pub per: Option<Hertz>,
#[cfg(stm32h7)]
pub rcc_pclk_d3: Option<Hertz>,
}
#[cfg(feature = "low-power")]