stm32: Add the ability to center-align timers
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70005c3956
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561126b0d6
@ -57,11 +57,12 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
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_ch4: Option<PwmPin<'d, T, Ch4>>,
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_ch4n: Option<ComplementaryPwmPin<'d, T, Ch4>>,
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freq: Hertz,
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counting_mode: CountingMode,
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) -> Self {
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Self::new_inner(tim, freq)
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Self::new_inner(tim, freq, counting_mode)
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}
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fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
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fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
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into_ref!(tim);
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T::enable();
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@ -70,6 +71,7 @@ impl<'d, T: ComplementaryCaptureCompare16bitInstance> ComplementaryPwm<'d, T> {
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let mut this = Self { inner: tim };
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this.inner.set_frequency(freq);
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this.inner.set_counting_mode(counting_mode);
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this.inner.start();
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this.inner.enable_outputs(true);
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@ -75,8 +75,16 @@ pub(crate) mod sealed {
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pub trait GeneralPurpose16bitInstance: Basic16bitInstance {
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fn regs_gp16() -> crate::pac::timer::TimGp16;
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fn set_count_direction(&mut self, direction: vals::Dir) {
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Self::regs_gp16().cr1().modify(|r| r.set_dir(direction));
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fn set_counting_mode(&mut self, mode: CountingMode) {
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let (cms, dir) = mode.values();
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let timer_enabled = Self::regs().cr1().read().cen();
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// Changing from edge aligned to center aligned (and vice versa) is not allowed while the timer is running.
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// Changing direction is discouraged while the timer is running.
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assert!(timer_enabled);
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Self::regs_gp16().cr1().modify(|r| r.set_dir(dir));
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Self::regs_gp16().cr1().modify(|r| r.set_cms(cms))
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}
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fn set_clock_division(&mut self, ckd: vals::Ckd) {
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@ -265,6 +273,43 @@ impl From<InputTISelection> for stm32_metapac::timer::vals::CcmrInputCcs {
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}
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}
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#[derive(Debug, Clone, Copy, PartialEq, Eq, Default)]
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pub enum CountingMode {
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#[default]
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/// The timer counts up to the reload value and then resets back to 0.
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EdgeAlignedUp,
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/// The timer counts down to 0 and then resets back to the reload value.
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EdgeAlignedDown,
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/// The timer counts up to the reload value and then counts back to 0.
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///
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/// The output compare interrupt flags of channels configured in output are
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/// set when the counter is counting down.
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CenterAlignedDownInterrupts,
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/// The timer counts up to the reload value and then counts back to 0.
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///
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/// The output compare interrupt flags of channels configured in output are
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/// set when the counter is counting up.
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CenterAlignedUpInterrupts,
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/// The timer counts up to the reload value and then counts back to 0.
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///
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/// The output compare interrupt flags of channels configured in output are
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/// set when the counter is counting both up or down.
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CenterAlignedBothInterrupts,
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}
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impl CountingMode {
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/// Get the register values to set the timer mode to the current variant
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pub fn values(&self) -> (vals::Cms, vals::Dir) {
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match self {
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CountingMode::EdgeAlignedUp => (vals::Cms::EDGEALIGNED, vals::Dir::UP),
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CountingMode::EdgeAlignedDown => (vals::Cms::EDGEALIGNED, vals::Dir::DOWN),
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CountingMode::CenterAlignedDownInterrupts => (vals::Cms::CENTERALIGNED1, vals::Dir::UP),
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CountingMode::CenterAlignedUpInterrupts => (vals::Cms::CENTERALIGNED2, vals::Dir::UP),
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CountingMode::CenterAlignedBothInterrupts => (vals::Cms::CENTERALIGNED3, vals::Dir::UP),
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}
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}
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}
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#[derive(Clone, Copy)]
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pub enum OutputCompareMode {
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Frozen,
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@ -56,11 +56,12 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
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_ch3: Option<PwmPin<'d, T, Ch3>>,
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_ch4: Option<PwmPin<'d, T, Ch4>>,
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freq: Hertz,
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counting_mode: CountingMode,
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) -> Self {
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Self::new_inner(tim, freq)
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Self::new_inner(tim, freq, counting_mode)
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}
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fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz) -> Self {
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fn new_inner(tim: impl Peripheral<P = T> + 'd, freq: Hertz, counting_mode: CountingMode) -> Self {
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into_ref!(tim);
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T::enable();
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@ -69,6 +70,7 @@ impl<'d, T: CaptureCompare16bitInstance> SimplePwm<'d, T> {
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let mut this = Self { inner: tim };
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this.inner.set_frequency(freq);
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this.inner.set_counting_mode(counting_mode);
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this.inner.start();
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this.inner.enable_outputs(true);
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