stm32/rcc: add better support for L4/L4+ differences.
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@ -58,7 +58,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-01a757e40df688efcda23607185640e1c2396ba9" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73e3f8a965a01fd5a168c3543b93ce49d475e130" }
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vcell = "0.1.3"
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bxcan = "0.7.0"
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nb = "1.0.0"
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@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-01a757e40df688efcda23607185640e1c2396ba9", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-73e3f8a965a01fd5a168c3543b93ce49d475e130", default-features = false, features = ["metadata"]}
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[features]
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@ -1,7 +1,8 @@
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use crate::pac::rcc::regs::Cfgr;
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use crate::pac::rcc::vals::Msirgsel;
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pub use crate::pac::rcc::vals::{
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Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul, Pllp as PllPDiv, Pllq as PllQDiv,
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Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
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Clk48sel as Clk48Src, Hpre as AHBPrescaler, Msirange as MSIRange, Pllm as PllPreDiv, Plln as PllMul,
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Pllp as PllPDiv, Pllq as PllQDiv, Pllr as PllRDiv, Pllsrc as PLLSource, Ppre as APBPrescaler, Sw as ClockSrc,
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};
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use crate::pac::{FLASH, RCC};
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use crate::rcc::{set_freqs, Clocks};
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@ -12,6 +13,9 @@ pub const HSI_FREQ: Hertz = Hertz(16_000_000);
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#[derive(Clone, Copy)]
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pub struct Pll {
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/// PLL source
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pub source: PLLSource,
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/// PLL pre-divider (DIVM).
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pub prediv: PllPreDiv,
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@ -32,11 +36,10 @@ pub struct Config {
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pub msi: Option<MSIRange>,
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pub hsi16: bool,
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pub hse: Option<Hertz>,
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#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
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#[cfg(not(any(stm32l47x, stm32l48x)))]
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pub hsi48: bool,
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// pll
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pub pll_src: PLLSource,
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pub pll: Option<Pll>,
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pub pllsai1: Option<Pll>,
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#[cfg(any(
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@ -50,6 +53,9 @@ pub struct Config {
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pub apb1_pre: APBPrescaler,
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pub apb2_pre: APBPrescaler,
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// muxes
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pub clk48_src: Clk48Src,
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// low speed LSI/LSE/RTC
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pub ls: super::LsConfig,
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}
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@ -65,7 +71,6 @@ impl Default for Config {
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ahb_pre: AHBPrescaler::DIV1,
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apb1_pre: APBPrescaler::DIV1,
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apb2_pre: APBPrescaler::DIV1,
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pll_src: PLLSource::NONE,
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pll: None,
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pllsai1: None,
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#[cfg(any(
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@ -73,7 +78,8 @@ impl Default for Config {
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))]
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pllsai2: None,
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#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
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hsi48: false,
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hsi48: true,
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clk48_src: Clk48Src::HSI48,
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ls: Default::default(),
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}
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}
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@ -84,7 +90,7 @@ pub(crate) unsafe fn init(config: Config) {
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if !RCC.cr().read().msion() {
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// Turn on MSI and configure it to 4MHz.
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RCC.cr().modify(|w| {
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w.set_msirgsel(true); // MSI Range is provided by MSIRANGE[3:0].
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w.set_msirgsel(Msirgsel::CR);
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w.set_msirange(MSIRange::RANGE4M);
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w.set_msipllen(false);
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w.set_msion(true)
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@ -106,7 +112,7 @@ pub(crate) unsafe fn init(config: Config) {
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// Enable MSI
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RCC.cr().write(|w| {
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w.set_msirange(range);
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w.set_msirgsel(true);
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w.set_msirgsel(Msirgsel::CR);
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w.set_msion(true);
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// If LSE is enabled, enable calibration of MSI
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@ -115,9 +121,7 @@ pub(crate) unsafe fn init(config: Config) {
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while !RCC.cr().read().msirdy() {}
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// Enable as clock source for USB, RNG if running at 48 MHz
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if range == MSIRange::RANGE48M {
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RCC.ccipr().modify(|w| w.set_clk48sel(0b11));
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}
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if range == MSIRange::RANGE48M {}
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msirange_to_hertz(range)
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});
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@ -136,154 +140,66 @@ pub(crate) unsafe fn init(config: Config) {
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freq
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});
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#[cfg(not(any(stm32l471, stm32l475, stm32l476, stm32l486)))]
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let _hsi48 = config.hsi48.then(|| {
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#[cfg(not(any(stm32l47x, stm32l48x)))]
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let hsi48 = config.hsi48.then(|| {
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RCC.crrcr().modify(|w| w.set_hsi48on(true));
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while !RCC.crrcr().read().hsi48rdy() {}
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// Enable as clock source for USB, RNG and SDMMC
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RCC.ccipr().modify(|w| w.set_clk48sel(0));
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Hertz(48_000_000)
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});
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#[cfg(any(stm32l47x, stm32l48x))]
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let hsi48 = None;
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let pll_src = match config.pll_src {
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PLLSource::NONE => None,
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PLLSource::HSE => hse,
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PLLSource::HSI16 => hsi16,
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PLLSource::MSI => msi,
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let _plls = [
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&config.pll,
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&config.pllsai1,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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&config.pllsai2,
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];
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// L4 has shared PLLSRC, PLLM, check it's equal in all PLLs.
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#[cfg(all(stm32l4, not(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))))]
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match get_equal(_plls.into_iter().flatten().map(|p| (p.source, p.prediv))) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some((source, prediv))) => RCC.pllcfgr().write(|w| {
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w.set_pllm(prediv);
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w.set_pllsrc(source);
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}),
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};
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let mut _pllp = None;
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let mut _pllq = None;
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let mut _pllr = None;
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if let Some(pll) = config.pll {
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let pll_src = pll_src.unwrap();
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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let vco_freq = pll_src / pll.prediv * pll.mul;
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_pllp = pll.divp.map(|div| vco_freq / div);
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_pllq = pll.divq.map(|div| vco_freq / div);
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_pllr = pll.divr.map(|div| vco_freq / div);
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RCC.pllcfgr().write(move |w| {
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w.set_plln(pll.mul);
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w.set_pllm(pll.prediv);
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w.set_pllsrc(config.pll_src);
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if let Some(divp) = pll.divp {
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w.set_pllp(divp);
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w.set_pllpen(true);
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}
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if let Some(divq) = pll.divq {
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w.set_pllq(divq);
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w.set_pllqen(true);
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}
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if let Some(divr) = pll.divr {
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w.set_pllr(divr);
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w.set_pllren(true);
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}
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});
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if _pllq == Some(Hertz(48_000_000)) {
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RCC.ccipr().modify(|w| w.set_clk48sel(0b10));
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}
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllon(true));
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while !RCC.cr().read().pllrdy() {}
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} else {
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// even if we're not using the main pll, set the source for pllsai
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RCC.pllcfgr().write(move |w| {
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w.set_pllsrc(config.pll_src);
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});
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}
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if let Some(pll) = config.pllsai1 {
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let pll_src = pll_src.unwrap();
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllsai1on(false));
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while RCC.cr().read().pllsai1rdy() {}
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let vco_freq = pll_src / pll.prediv * pll.mul;
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let _pllp = pll.divp.map(|div| vco_freq / div);
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let _pllq = pll.divq.map(|div| vco_freq / div);
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let _pllr = pll.divr.map(|div| vco_freq / div);
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RCC.pllsai1cfgr().write(move |w| {
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w.set_plln(pll.mul);
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w.set_pllm(pll.prediv);
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if let Some(divp) = pll.divp {
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w.set_pllp(divp);
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w.set_pllpen(true);
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}
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if let Some(divq) = pll.divq {
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w.set_pllq(divq);
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w.set_pllqen(true);
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}
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if let Some(divr) = pll.divr {
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w.set_pllr(divr);
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w.set_pllren(true);
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}
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});
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if _pllq == Some(Hertz(48_000_000)) {
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RCC.ccipr().modify(|w| w.set_clk48sel(0b01));
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}
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllsai1on(true));
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while !RCC.cr().read().pllsai1rdy() {}
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}
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// L4+ has shared PLLSRC, check it's equal in all PLLs.
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
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match get_equal(_plls.into_iter().flatten().map(|p| p.source)) {
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Err(()) => panic!("Source must be equal across all enabled PLLs."),
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Ok(None) => {}
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Ok(Some(source)) => RCC.pllcfgr().write(|w| {
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w.set_pllsrc(source);
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}),
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};
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let pll_input = PllInput { hse, hsi16, msi };
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let pll = init_pll(PllInstance::Pll, config.pll, &pll_input);
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let pllsai1 = init_pll(PllInstance::Pllsai1, config.pllsai1, &pll_input);
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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if let Some(pll) = config.pllsai2 {
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let pll_src = pll_src.unwrap();
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// Disable PLL
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RCC.cr().modify(|w| w.set_pllsai2on(false));
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while RCC.cr().read().pllsai2rdy() {}
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let vco_freq = pll_src / pll.prediv * pll.mul;
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let _pllp = pll.divp.map(|div| vco_freq / div);
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let _pllq = pll.divq.map(|div| vco_freq / div);
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let _pllr = pll.divr.map(|div| vco_freq / div);
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RCC.pllsai2cfgr().write(move |w| {
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w.set_plln(pll.mul);
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w.set_pllm(pll.prediv);
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if let Some(divp) = pll.divp {
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w.set_pllp(divp);
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w.set_pllpen(true);
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}
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if let Some(divq) = pll.divq {
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w.set_pllq(divq);
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w.set_pllqen(true);
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}
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if let Some(divr) = pll.divr {
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w.set_pllr(divr);
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w.set_pllren(true);
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}
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});
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// Enable PLL
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RCC.cr().modify(|w| w.set_pllsai2on(true));
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while !RCC.cr().read().pllsai2rdy() {}
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}
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let _pllsai2 = init_pll(PllInstance::Pllsai2, config.pllsai2, &pll_input);
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let sys_clk = match config.mux {
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ClockSrc::HSE => hse.unwrap(),
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ClockSrc::HSI16 => hsi16.unwrap(),
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ClockSrc::MSI => msi.unwrap(),
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ClockSrc::PLL => _pllr.unwrap(),
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ClockSrc::PLL => pll._r.unwrap(),
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};
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let _clk48 = match config.clk48_src {
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Clk48Src::HSI48 => hsi48,
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Clk48Src::MSI => msi,
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Clk48Src::PLLSAI1_Q => pllsai1._q,
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Clk48Src::PLL_Q => pll._q,
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};
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#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx))]
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@ -357,3 +273,136 @@ fn msirange_to_hertz(range: MSIRange) -> Hertz {
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_ => unreachable!(),
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}
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}
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fn get_equal<T: Eq>(mut iter: impl Iterator<Item = T>) -> Result<Option<T>, ()> {
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let Some(x) = iter.next() else { return Ok(None) };
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if !iter.all(|y| y == x) {
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return Err(());
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}
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return Ok(Some(x));
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}
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struct PllInput {
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hsi16: Option<Hertz>,
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hse: Option<Hertz>,
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msi: Option<Hertz>,
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}
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#[derive(Default)]
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struct PllOutput {
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_p: Option<Hertz>,
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_q: Option<Hertz>,
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_r: Option<Hertz>,
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}
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#[derive(PartialEq, Eq, Clone, Copy)]
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enum PllInstance {
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Pll,
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Pllsai1,
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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Pllsai2,
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}
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fn init_pll(instance: PllInstance, config: Option<Pll>, input: &PllInput) -> PllOutput {
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// Disable PLL
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match instance {
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PllInstance::Pll => {
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RCC.cr().modify(|w| w.set_pllon(false));
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while RCC.cr().read().pllrdy() {}
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}
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PllInstance::Pllsai1 => {
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RCC.cr().modify(|w| w.set_pllsai1on(false));
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while RCC.cr().read().pllsai1rdy() {}
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}
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#[cfg(any(
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stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
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))]
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PllInstance::Pllsai2 => {
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RCC.cr().modify(|w| w.set_pllsai2on(false));
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while RCC.cr().read().pllsai2rdy() {}
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}
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}
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let Some(pll) = config else { return PllOutput::default() };
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let pll_src = match pll.source {
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PLLSource::NONE => panic!("must not select PLL source as NONE"),
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PLLSource::HSE => input.hse,
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PLLSource::HSI16 => input.hsi16,
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PLLSource::MSI => input.msi,
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};
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let pll_src = pll_src.unwrap();
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let vco_freq = pll_src / pll.prediv * pll.mul;
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let p = pll.divp.map(|div| vco_freq / div);
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let q = pll.divq.map(|div| vco_freq / div);
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let r = pll.divr.map(|div| vco_freq / div);
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macro_rules! write_fields {
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($w:ident) => {
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$w.set_plln(pll.mul);
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if let Some(divp) = pll.divp {
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$w.set_pllp(divp);
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$w.set_pllpen(true);
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}
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if let Some(divq) = pll.divq {
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$w.set_pllq(divq);
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$w.set_pllqen(true);
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}
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if let Some(divr) = pll.divr {
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$w.set_pllr(divr);
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$w.set_pllren(true);
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}
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};
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}
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match instance {
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PllInstance::Pll => RCC.pllcfgr().write(|w| {
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w.set_pllm(pll.prediv);
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w.set_pllsrc(pll.source);
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write_fields!(w);
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||||
}),
|
||||
PllInstance::Pllsai1 => RCC.pllsai1cfgr().write(|w| {
|
||||
#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx, stm32l5))]
|
||||
w.set_pllm(pll.prediv);
|
||||
#[cfg(stm32l5)]
|
||||
w.set_pllsrc(pll.source);
|
||||
write_fields!(w);
|
||||
}),
|
||||
#[cfg(any(
|
||||
stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
|
||||
))]
|
||||
PllInstance::Pllsai2 => RCC.pllsai2cfgr().write(|w| {
|
||||
#[cfg(any(stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx, stm32l5))]
|
||||
w.set_pllm(pll.prediv);
|
||||
#[cfg(stm32l5)]
|
||||
w.set_pllsrc(pll.source);
|
||||
write_fields!(w);
|
||||
}),
|
||||
}
|
||||
|
||||
// Enable PLL
|
||||
match instance {
|
||||
PllInstance::Pll => {
|
||||
RCC.cr().modify(|w| w.set_pllon(true));
|
||||
while !RCC.cr().read().pllrdy() {}
|
||||
}
|
||||
PllInstance::Pllsai1 => {
|
||||
RCC.cr().modify(|w| w.set_pllsai1on(true));
|
||||
while !RCC.cr().read().pllsai1rdy() {}
|
||||
}
|
||||
#[cfg(any(
|
||||
stm32l47x, stm32l48x, stm32l49x, stm32l4ax, stm32l4px, stm32l4qx, stm32l4rx, stm32l4sx
|
||||
))]
|
||||
PllInstance::Pllsai2 => {
|
||||
RCC.cr().modify(|w| w.set_pllsai2on(true));
|
||||
while !RCC.cr().read().pllsai2rdy() {}
|
||||
}
|
||||
}
|
||||
|
||||
PllOutput { _p: p, _q: q, _r: r }
|
||||
}
|
||||
|
@ -104,7 +104,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
// Enable as clock source for USB, RNG if running at 48 MHz
|
||||
if range == MSIRange::RANGE48M {
|
||||
RCC.ccipr1().modify(|w| {
|
||||
w.set_clk48msel(0b11);
|
||||
w.set_clk48sel(0b11);
|
||||
});
|
||||
}
|
||||
(msirange_to_hertz(range), Sw::MSI)
|
||||
@ -173,7 +173,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
let freq = src_freq / prediv * mul / divq;
|
||||
assert!(freq.0 == 48_000_000);
|
||||
RCC.ccipr1().modify(|w| {
|
||||
w.set_clk48msel(0b10);
|
||||
w.set_clk48sel(0b10);
|
||||
});
|
||||
}
|
||||
|
||||
@ -191,7 +191,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
let freq = src_freq / prediv * mul / q_div;
|
||||
if freq.0 == 48_000_000 {
|
||||
RCC.ccipr1().modify(|w| {
|
||||
w.set_clk48msel(0b1);
|
||||
w.set_clk48sel(0b1);
|
||||
});
|
||||
}
|
||||
}
|
||||
@ -218,7 +218,7 @@ pub(crate) unsafe fn init(config: Config) {
|
||||
while !RCC.crrcr().read().hsi48rdy() {}
|
||||
|
||||
// Enable as clock source for USB, RNG and SDMMC
|
||||
RCC.ccipr1().modify(|w| w.set_clk48msel(0));
|
||||
RCC.ccipr1().modify(|w| w.set_clk48sel(0));
|
||||
}
|
||||
|
||||
// Set flash wait states
|
||||
|
@ -20,7 +20,7 @@ pub use mco::*;
|
||||
#[cfg_attr(rcc_g4, path = "g4.rs")]
|
||||
#[cfg_attr(any(rcc_h5, rcc_h50, rcc_h7, rcc_h7rm0433, rcc_h7ab), path = "h.rs")]
|
||||
#[cfg_attr(any(rcc_l0, rcc_l0_v2, rcc_l1), path = "l0l1.rs")]
|
||||
#[cfg_attr(rcc_l4, path = "l4.rs")]
|
||||
#[cfg_attr(any(rcc_l4, rcc_l4plus), path = "l4.rs")]
|
||||
#[cfg_attr(rcc_l5, path = "l5.rs")]
|
||||
#[cfg_attr(rcc_u5, path = "u5.rs")]
|
||||
#[cfg_attr(rcc_wb, path = "wb.rs")]
|
||||
@ -65,6 +65,7 @@ pub struct Clocks {
|
||||
pub hclk1: Hertz,
|
||||
#[cfg(any(
|
||||
rcc_l4,
|
||||
rcc_l4plus,
|
||||
rcc_l5,
|
||||
rcc_f2,
|
||||
rcc_f4,
|
||||
@ -85,6 +86,7 @@ pub struct Clocks {
|
||||
pub hclk2: Hertz,
|
||||
#[cfg(any(
|
||||
rcc_l4,
|
||||
rcc_l4plus,
|
||||
rcc_l5,
|
||||
rcc_f2,
|
||||
rcc_f4,
|
||||
|
@ -13,7 +13,7 @@ fn main() -> ! {
|
||||
info!("Hello World!");
|
||||
|
||||
pac::RCC.ccipr().modify(|w| {
|
||||
w.set_adcsel(0b11);
|
||||
w.set_adcsel(pac::rcc::vals::Adcsel::SYSCLK);
|
||||
});
|
||||
pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));
|
||||
|
||||
|
@ -18,8 +18,8 @@ async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.rcc.mux = ClockSrc::PLL;
|
||||
config.rcc.hsi16 = true;
|
||||
config.rcc.pll_src = PLLSource::HSI16;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PLLSource::HSI16,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL18,
|
||||
divp: None,
|
||||
|
@ -17,8 +17,8 @@ async fn main(_spawner: Spawner) {
|
||||
let mut config = Config::default();
|
||||
config.rcc.mux = ClockSrc::PLL;
|
||||
config.rcc.hse = Some(Hertz::mhz(8));
|
||||
config.rcc.pll_src = PLLSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PLLSource::HSE,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL20,
|
||||
divp: None,
|
||||
|
@ -79,8 +79,8 @@ async fn main(spawner: Spawner) {
|
||||
// 80MHz highest frequency for flash 0 wait.
|
||||
config.rcc.mux = ClockSrc::PLL;
|
||||
config.rcc.hse = Some(Hertz::mhz(8));
|
||||
config.rcc.pll_src = PLLSource::HSE;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PLLSource::HSE,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL20,
|
||||
divp: None,
|
||||
|
@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
|
||||
config.rcc.hsi48 = true;
|
||||
config.rcc.mux = ClockSrc::PLL;
|
||||
config.rcc.hsi16 = true;
|
||||
config.rcc.pll_src = PLLSource::HSI16;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PLLSource::HSI16,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL10,
|
||||
divp: None,
|
||||
|
@ -289,8 +289,8 @@ pub fn config() -> Config {
|
||||
use embassy_stm32::rcc::*;
|
||||
config.rcc.mux = ClockSrc::PLL;
|
||||
config.rcc.hsi16 = true;
|
||||
config.rcc.pll_src = PLLSource::HSI16;
|
||||
config.rcc.pll = Some(Pll {
|
||||
source: PLLSource::HSI16,
|
||||
prediv: PllPreDiv::DIV1,
|
||||
mul: PllMul::MUL18,
|
||||
divp: None,
|
||||
|
Loading…
Reference in New Issue
Block a user