max/embassy
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

stm32/rcc: add better support for L4/L4+ differences.

Browse Source
This commit is contained in:
Dario Nieuwenhuis
2023-10-16 03:09:33 +02:00
parent f54753beaa
commit 5c5e681819
10 changed files with 206 additions and 155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
examples/stm32l4/src/bin/adc.rs
View File

@ -13,7 +13,7 @@ fn main() -> ! {
info!("Hello World!");
pac::RCC.ccipr().modify(|w| {
w.set_adcsel(0b11);
w.set_adcsel(pac::rcc::vals::Adcsel::SYSCLK);
});
pac::RCC.ahb2enr().modify(|w| w.set_adcen(true));

2
examples/stm32l4/src/bin/rng.rs
View File

@ -18,8 +18,8 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.mux = ClockSrc::PLL;
config.rcc.hsi16 = true;
config.rcc.pll_src = PLLSource::HSI16;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI16,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL18,
divp: None,

2
examples/stm32l4/src/bin/rtc.rs
View File

@ -17,8 +17,8 @@ async fn main(_spawner: Spawner) {
let mut config = Config::default();
config.rcc.mux = ClockSrc::PLL;
config.rcc.hse = Some(Hertz::mhz(8));
config.rcc.pll_src = PLLSource::HSE;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,

2
examples/stm32l4/src/bin/spe_adin1110_http_server.rs
View File

@ -79,8 +79,8 @@ async fn main(spawner: Spawner) {
// 80MHz highest frequency for flash 0 wait.
config.rcc.mux = ClockSrc::PLL;
config.rcc.hse = Some(Hertz::mhz(8));
config.rcc.pll_src = PLLSource::HSE;
config.rcc.pll = Some(Pll {
source: PLLSource::HSE,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL20,
divp: None,

2
examples/stm32l4/src/bin/usb_serial.rs
View File

@ -26,8 +26,8 @@ async fn main(_spawner: Spawner) {
config.rcc.hsi48 = true;
config.rcc.mux = ClockSrc::PLL;
config.rcc.hsi16 = true;
config.rcc.pll_src = PLLSource::HSI16;
config.rcc.pll = Some(Pll {
source: PLLSource::HSI16,
prediv: PllPreDiv::DIV1,
mul: PllMul::MUL10,
divp: None,