f4-pll: Add max values per chip
This commit is contained in:
Thales Fragoso
parent
e7714983b3
commit
5cfb9adad8
268
embassy-stm32/src/rcc/f4/max.rs
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268
embassy-stm32/src/rcc/f4/max.rs
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@ -0,0 +1,268 @@
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#[cfg(any(
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feature = "stm32f401cb",
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feature = "stm32f401cc",
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feature = "stm32f401cd",
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feature = "stm32f401ce",
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feature = "stm32f401rb",
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feature = "stm32f401rc",
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feature = "stm32f401rd",
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feature = "stm32f401re",
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feature = "stm32f401vb",
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feature = "stm32f401vc",
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feature = "stm32f401vd",
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feature = "stm32f401ve",
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))]
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pub(crate) const SYSCLK_MAX: u32 = 84_000_000;
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#[cfg(any(
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feature = "stm32f405oe",
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feature = "stm32f405og",
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feature = "stm32f405rg",
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feature = "stm32f405vg",
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feature = "stm32f405zg",
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feature = "stm32f407ie",
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feature = "stm32f407ig",
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feature = "stm32f407ve",
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feature = "stm32f407vg",
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feature = "stm32f407ze",
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feature = "stm32f407zg",
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feature = "stm32f415og",
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feature = "stm32f415rg",
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feature = "stm32f415vg",
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feature = "stm32f415zg",
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feature = "stm32f417ie",
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feature = "stm32f417ig",
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feature = "stm32f417ve",
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feature = "stm32f417vg",
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feature = "stm32f417ze",
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feature = "stm32f417zg",
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))]
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pub(crate) const SYSCLK_MAX: u32 = 168_000_000;
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#[cfg(any(
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feature = "stm32f410c8",
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feature = "stm32f410cb",
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feature = "stm32f410r8",
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feature = "stm32f410rb",
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feature = "stm32f410t8",
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feature = "stm32f410tb",
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feature = "stm32f411cc",
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feature = "stm32f411ce",
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feature = "stm32f411rc",
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feature = "stm32f411re",
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feature = "stm32f411vc",
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feature = "stm32f411ve",
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feature = "stm32f412ce",
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feature = "stm32f412cg",
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feature = "stm32f412re",
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feature = "stm32f412rg",
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feature = "stm32f412ve",
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feature = "stm32f412vg",
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feature = "stm32f412ze",
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feature = "stm32f412zg",
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feature = "stm32f413cg",
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feature = "stm32f413ch",
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feature = "stm32f413mg",
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feature = "stm32f413mh",
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feature = "stm32f413rg",
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feature = "stm32f413rh",
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feature = "stm32f413vg",
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feature = "stm32f413vh",
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feature = "stm32f413zg",
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feature = "stm32f413zh",
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feature = "stm32f423ch",
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feature = "stm32f423mh",
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feature = "stm32f423rh",
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feature = "stm32f423vh",
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feature = "stm32f423zh",
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))]
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pub(crate) const SYSCLK_MAX: u32 = 100_000_000;
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#[cfg(any(
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feature = "stm32f427ag",
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feature = "stm32f427ai",
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feature = "stm32f427ig",
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feature = "stm32f427ii",
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feature = "stm32f427vg",
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feature = "stm32f427vi",
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feature = "stm32f427zg",
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feature = "stm32f427zi",
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feature = "stm32f429ag",
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feature = "stm32f429ai",
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feature = "stm32f429be",
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feature = "stm32f429bg",
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feature = "stm32f429bi",
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feature = "stm32f429ie",
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feature = "stm32f429ig",
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feature = "stm32f429ii",
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feature = "stm32f429ne",
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feature = "stm32f429ng",
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feature = "stm32f429ni",
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feature = "stm32f429ve",
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feature = "stm32f429vg",
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feature = "stm32f429vi",
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feature = "stm32f429ze",
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feature = "stm32f429zg",
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feature = "stm32f429zi",
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feature = "stm32f437ai",
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feature = "stm32f437ig",
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feature = "stm32f437ii",
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feature = "stm32f437vg",
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feature = "stm32f437vi",
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feature = "stm32f437zg",
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feature = "stm32f437zi",
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feature = "stm32f439ai",
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feature = "stm32f439bg",
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feature = "stm32f439bi",
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feature = "stm32f439ig",
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feature = "stm32f439ii",
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feature = "stm32f439ng",
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feature = "stm32f439ni",
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feature = "stm32f439vg",
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feature = "stm32f439vi",
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feature = "stm32f439zg",
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feature = "stm32f439zi",
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feature = "stm32f446mc",
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feature = "stm32f446me",
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feature = "stm32f446rc",
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feature = "stm32f446re",
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feature = "stm32f446vc",
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feature = "stm32f446ve",
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feature = "stm32f446zc",
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feature = "stm32f446ze",
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feature = "stm32f469ae",
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feature = "stm32f469ag",
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feature = "stm32f469ai",
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feature = "stm32f469be",
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feature = "stm32f469bg",
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feature = "stm32f469bi",
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feature = "stm32f469ie",
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feature = "stm32f469ig",
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feature = "stm32f469ii",
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feature = "stm32f469ne",
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feature = "stm32f469ng",
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feature = "stm32f469ni",
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feature = "stm32f469ve",
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feature = "stm32f469vg",
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feature = "stm32f469vi",
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feature = "stm32f469ze",
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feature = "stm32f469zg",
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feature = "stm32f469zi",
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feature = "stm32f479ag",
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feature = "stm32f479ai",
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feature = "stm32f479bg",
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feature = "stm32f479bi",
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feature = "stm32f479ig",
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feature = "stm32f479ii",
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feature = "stm32f479ng",
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feature = "stm32f479ni",
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feature = "stm32f479vg",
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feature = "stm32f479vi",
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feature = "stm32f479zg",
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feature = "stm32f479zi",
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))]
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pub(crate) const SYSCLK_MAX: u32 = 180_000_000;
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#[cfg(any(
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feature = "stm32f401cb",
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feature = "stm32f401cc",
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feature = "stm32f401cd",
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feature = "stm32f401ce",
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feature = "stm32f401rb",
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feature = "stm32f401rc",
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feature = "stm32f401rd",
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feature = "stm32f401re",
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feature = "stm32f401vb",
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feature = "stm32f401vc",
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feature = "stm32f401vd",
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feature = "stm32f401ve",
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feature = "stm32f410c8",
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feature = "stm32f410cb",
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feature = "stm32f410r8",
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feature = "stm32f410rb",
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feature = "stm32f410t8",
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feature = "stm32f410tb",
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feature = "stm32f411cc",
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feature = "stm32f411ce",
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feature = "stm32f411rc",
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feature = "stm32f411re",
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feature = "stm32f411vc",
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feature = "stm32f411ve",
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feature = "stm32f412ce",
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feature = "stm32f412cg",
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feature = "stm32f412re",
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feature = "stm32f412rg",
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feature = "stm32f412ve",
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feature = "stm32f412vg",
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feature = "stm32f412ze",
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feature = "stm32f412zg",
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feature = "stm32f413cg",
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feature = "stm32f413ch",
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feature = "stm32f413mg",
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feature = "stm32f413mh",
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feature = "stm32f413rg",
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feature = "stm32f413rh",
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feature = "stm32f413vg",
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feature = "stm32f413vh",
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feature = "stm32f413zg",
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feature = "stm32f413zh",
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feature = "stm32f423ch",
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feature = "stm32f423mh",
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feature = "stm32f423rh",
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feature = "stm32f423vh",
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feature = "stm32f423zh",
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))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX;
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#[cfg(not(any(
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feature = "stm32f401cb",
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feature = "stm32f401cc",
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feature = "stm32f401cd",
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feature = "stm32f401ce",
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feature = "stm32f401rb",
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feature = "stm32f401rc",
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feature = "stm32f401rd",
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feature = "stm32f401re",
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feature = "stm32f401vb",
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feature = "stm32f401vc",
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feature = "stm32f401vd",
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feature = "stm32f401ve",
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feature = "stm32f410c8",
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feature = "stm32f410cb",
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feature = "stm32f410r8",
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feature = "stm32f410rb",
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feature = "stm32f410t8",
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feature = "stm32f410tb",
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feature = "stm32f411cc",
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feature = "stm32f411ce",
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feature = "stm32f411rc",
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feature = "stm32f411re",
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feature = "stm32f411vc",
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feature = "stm32f411ve",
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feature = "stm32f412ce",
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feature = "stm32f412cg",
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feature = "stm32f412re",
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feature = "stm32f412rg",
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feature = "stm32f412ve",
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feature = "stm32f412vg",
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feature = "stm32f412ze",
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feature = "stm32f412zg",
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feature = "stm32f413cg",
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feature = "stm32f413ch",
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feature = "stm32f413mg",
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feature = "stm32f413mh",
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feature = "stm32f413rg",
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feature = "stm32f413rh",
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feature = "stm32f413vg",
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feature = "stm32f413vh",
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feature = "stm32f413zg",
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feature = "stm32f413zh",
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feature = "stm32f423ch",
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feature = "stm32f423mh",
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feature = "stm32f423rh",
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feature = "stm32f423vh",
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feature = "stm32f423zh",
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)))]
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pub(crate) const PCLK2_MAX: u32 = SYSCLK_MAX / 2;
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pub(crate) const PCLK1_MAX: u32 = PCLK2_MAX / 2;
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@ -5,13 +5,10 @@ use crate::time::Hertz;
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use core::marker::PhantomData;
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use embassy::util::Unborrow;
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const HSI: u32 = 16_000_000;
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mod max;
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use max::{PCLK1_MAX, PCLK2_MAX};
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// TODO: This is for the F401, find a way to make it compile time configurable
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const SYSCLK_MIN: u32 = 24_000_000;
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const SYSCLK_MAX: u32 = 84_000_000;
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const PCLK2_MAX: u32 = SYSCLK_MAX;
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const PCLK1_MAX: u32 = PCLK2_MAX / 2;
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const HSI: u32 = 16_000_000;
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/// Clocks configutation
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#[non_exhaustive]
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@ -69,7 +66,6 @@ impl<'d> Rcc<'d> {
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} else {
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sysclk
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};
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assert!((SYSCLK_MIN..=SYSCLK_MAX).contains(&sysclk), "sysclk");
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let hclk = self.config.hclk.map(|h| h.0).unwrap_or(sysclk);
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let (hpre_bits, hpre_div) = match (sysclk + hclk - 1) / hclk {
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@ -247,7 +243,7 @@ impl<'d> Rcc<'d> {
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.unwrap();
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let vco_in = pllsrcclk / pllm;
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assert!((1_000_000..=2_000_000).contains(&vco_in), "vco_in");
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assert!((1_000_000..=2_000_000).contains(&vco_in));
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// Main scaler, must result in >= 100MHz (>= 192MHz for F401)
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// and <= 432MHz, min 50, max 432
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@ -266,10 +262,6 @@ impl<'d> Rcc<'d> {
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} else {
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sysclk * sysclk_div / vco_in
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};
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assert!(
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(192_000_000..=432_000_000).contains(&(vco_in * plln)),
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"plln"
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);
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let pllp = (sysclk_div / 2) - 1;
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@ -19,7 +19,7 @@ mod example_common;
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fn config() -> Config {
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let mut rcc_config = RccConfig::default();
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rcc_config.sys_ck = Some(Hertz(32_000_000));
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rcc_config.sys_ck = Some(Hertz(84_000_000));
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rcc_config.enable_debug_wfe = true;
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Config::default().rcc(rcc_config)
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