Merge pull request #22 from danbev/antdiv-const
Add const for IOCTL ANTDIV
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commit
6b35f654ba
@ -138,6 +138,7 @@ const IRQ_F3_INTR: u16 = 0x8000;
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const IOCTL_CMD_UP: u32 = 2;
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const IOCTL_CMD_UP: u32 = 2;
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const IOCTL_CMD_SET_SSID: u32 = 26;
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const IOCTL_CMD_SET_SSID: u32 = 26;
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const IOCTL_CMD_ANTDIV: u32 = 64;
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const IOCTL_CMD_SET_VAR: u32 = 263;
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const IOCTL_CMD_SET_VAR: u32 = 263;
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const IOCTL_CMD_GET_VAR: u32 = 262;
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const IOCTL_CMD_GET_VAR: u32 = 262;
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const IOCTL_CMD_SET_PASSPHRASE: u32 = 268;
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const IOCTL_CMD_SET_PASSPHRASE: u32 = 268;
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@ -317,7 +318,8 @@ impl<'a> Control<'a> {
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// set country takes some time, next ioctls fail if we don't wait.
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// set country takes some time, next ioctls fail if we don't wait.
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Timer::after(Duration::from_millis(100)).await;
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Timer::after(Duration::from_millis(100)).await;
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self.ioctl_set_u32(64, 0, 0).await; // WLC_SET_ANTDIV
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// Set antenna to chip antenna
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self.ioctl_set_u32(IOCTL_CMD_ANTDIV, 0, 0).await;
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self.set_iovar_u32("bus:txglom", 0).await;
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self.set_iovar_u32("bus:txglom", 0).await;
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Timer::after(Duration::from_millis(100)).await;
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Timer::after(Duration::from_millis(100)).await;
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