i2c-v2: Simplify write_dma
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@ -391,8 +391,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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bytes: &[u8],
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first_slice: bool,
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last_slice: bool,
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next_slice_len: usize,
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next_is_last: bool,
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) -> Result<(), Error>
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where
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TXDMA: crate::i2c::TxDma<T>,
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@ -443,6 +441,11 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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(total_chunks != 1) || !last_slice,
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);
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}
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} else {
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_continue(total_len.min(255), (total_chunks != 1) || !last_slice);
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}
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}
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poll_fn(|cx| {
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@ -450,17 +453,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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let chunks_transferred = STATE.chunks_transferred[state_number].load(Ordering::Relaxed);
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if chunks_transferred == total_chunks {
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if !last_slice {
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// NOTE(unsafe) self.tx_dma does not fiddle with the i2c registers
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unsafe {
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Self::master_continue(
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next_slice_len.min(255),
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(next_slice_len > 255) || !next_is_last,
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);
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T::regs().cr1().modify(|w| w.set_tcie(true));
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}
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}
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return Poll::Ready(());
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} else if chunks_transferred != 0 {
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remaining_len = remaining_len.saturating_sub(255);
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@ -490,8 +482,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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where
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TXDMA: crate::i2c::TxDma<T>,
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{
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self.write_dma_internal(address, bytes, true, true, 0, true)
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.await
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self.write_dma_internal(address, bytes, true, true).await
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}
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pub async fn write_dma_vectored(&mut self, address: u8, bytes: &[&[u8]]) -> Result<(), Error>
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@ -501,21 +492,15 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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if bytes.is_empty() {
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return Err(Error::ZeroLengthTransfer);
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}
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let mut iter = bytes.iter().peekable();
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let mut iter = bytes.iter();
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let mut first = true;
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let mut current = iter.next();
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while let Some(c) = current {
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let next = iter.next();
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let (next_len, is_last) = if let Some(next) = next {
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(next.len(), false)
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} else {
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(0, true)
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};
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let next_is_last = iter.peek().is_none();
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let is_last = next.is_none();
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self.write_dma_internal(address, c, first, is_last, next_len, next_is_last)
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.await?;
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self.write_dma_internal(address, c, first, is_last).await?;
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first = false;
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current = next;
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}
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