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fix(rp): spi transfer

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Signed-off-by: Lachezar Lechev <elpiel93@gmail.com>
This commit is contained in:
Lachezar Lechev 2023-03-20 16:34:30 +02:00
parent b6663a013f
commit 7a4db1da26
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GPG Key ID: B2D641D6A2C8E742
2 changed files with 41 additions and 6 deletions
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1
embassy-rp/src/dma.rs
View File

@ -1,3 +1,4 @@
//! Direct Memory Access (DMA)
use core::future::Future;
use core::pin::Pin;
use core::sync::atomic::{compiler_fence, Ordering};

42
embassy-rp/src/spi.rs
View File

@ -1,3 +1,4 @@
//! Serial Peripheral Interface
use core::marker::PhantomData;
use embassy_embedded_hal::SetConfig;
@ -385,19 +386,36 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
async fn transfer_inner(&mut self, rx_ptr: *mut [u8], tx_ptr: *const [u8]) -> Result<(), Error> {
let (_, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
let (_, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
assert_eq!(from_len, to_len);
unsafe {
self.inner.regs().dmacr().write(|reg| {
reg.set_rxdmae(true);
reg.set_txdmae(true);
})
};
let tx_ch = self.tx_dma.as_mut().unwrap();
let tx_transfer = unsafe {
let mut tx_ch = self.tx_dma.as_mut().unwrap();
// If we don't assign future to a variable, the data register pointer
// is held across an await and makes the future non-Send.
crate::dma::write(tx_ch, tx_ptr, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
let tx_transfer = async {
let p = self.inner.regs();
unsafe {
crate::dma::write(&mut tx_ch, tx_ptr, p.dr().ptr() as *mut _, T::TX_DREQ).await;
if from_len > to_len {
let write_bytes_len = from_len - to_len;
// disable incrementation of buffer
tx_ch.regs().ctrl_trig().modify(|ctrl_trig| {
ctrl_trig.set_incr_write(false);
ctrl_trig.set_incr_read(false);
});
// write dummy data
crate::dma::write_repeated(tx_ch, p.dr().ptr() as *mut u8, write_bytes_len, T::TX_DREQ).await
}
}
};
let rx_ch = self.rx_dma.as_mut().unwrap();
let rx_transfer = unsafe {
// If we don't assign future to a variable, the data register pointer
@ -405,6 +423,22 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
};
join(tx_transfer, rx_transfer).await;
// if tx > rx we should clear any overflow of the FIFO SPI buffer
if from_len > to_len {
let p = self.inner.regs();
unsafe {
while p.sr().read().bsy() {}
// clear RX FIFO contents to prevent stale reads
while p.sr().read().rne() {
let _: u16 = p.dr().read().data();
}
// clear RX overrun interrupt
p.icr().write(|w| w.set_roric(true));
}
}
Ok(())
}
}