stm32: codegen interrupts
This commit is contained in:
Dario Nieuwenhuis
@ -15,6 +15,427 @@ peripherals!(
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);
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pub const GPIO_BASE: usize = 0x40020000;
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pub const GPIO_STRIDE: usize = 0x400;
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pub mod interrupt {
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pub use cortex_m::interrupt::{CriticalSection, Mutex};
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pub use embassy::interrupt::{declare, take, Interrupt};
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pub use embassy_extras::interrupt::Priority4 as Priority;
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#[derive(Copy, Clone, Debug, PartialEq, Eq)]
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#[allow(non_camel_case_types)]
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enum InterruptEnum {
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ADC = 18,
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CAN1_RX0 = 20,
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CAN1_RX1 = 21,
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CAN1_SCE = 22,
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CAN1_TX = 19,
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CAN2_RX0 = 64,
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CAN2_RX1 = 65,
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CAN2_SCE = 66,
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CAN2_TX = 63,
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DFSDM1_FLT0 = 61,
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DFSDM1_FLT1 = 62,
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DMA1_Stream0 = 11,
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DMA1_Stream1 = 12,
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DMA1_Stream2 = 13,
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DMA1_Stream3 = 14,
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DMA1_Stream4 = 15,
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DMA1_Stream5 = 16,
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DMA1_Stream6 = 17,
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DMA1_Stream7 = 47,
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DMA2_Stream0 = 56,
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DMA2_Stream1 = 57,
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DMA2_Stream2 = 58,
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DMA2_Stream3 = 59,
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DMA2_Stream4 = 60,
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DMA2_Stream5 = 68,
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DMA2_Stream6 = 69,
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DMA2_Stream7 = 70,
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EXTI0 = 6,
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EXTI1 = 7,
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EXTI15_10 = 40,
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EXTI2 = 8,
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EXTI3 = 9,
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EXTI4 = 10,
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EXTI9_5 = 23,
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FLASH = 4,
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FMPI2C1_ER = 96,
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FMPI2C1_EV = 95,
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FPU = 81,
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I2C1_ER = 32,
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I2C1_EV = 31,
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I2C2_ER = 34,
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I2C2_EV = 33,
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I2C3_ER = 73,
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I2C3_EV = 72,
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OTG_FS = 67,
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OTG_FS_WKUP = 42,
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PVD = 1,
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QUADSPI = 92,
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RCC = 5,
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RNG = 80,
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RTC_Alarm = 41,
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RTC_WKUP = 3,
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SDIO = 49,
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SPI1 = 35,
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SPI2 = 36,
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SPI3 = 51,
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SPI4 = 84,
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SPI5 = 85,
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TAMP_STAMP = 2,
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TIM1_BRK_TIM9 = 24,
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TIM1_CC = 27,
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TIM1_TRG_COM_TIM11 = 26,
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TIM1_UP_TIM10 = 25,
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TIM2 = 28,
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TIM3 = 29,
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TIM4 = 30,
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TIM5 = 50,
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TIM6 = 54,
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TIM7 = 55,
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TIM8_BRK_TIM12 = 43,
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TIM8_CC = 46,
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TIM8_TRG_COM_TIM14 = 45,
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TIM8_UP_TIM13 = 44,
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USART1 = 37,
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USART2 = 38,
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USART3 = 39,
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USART6 = 71,
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WWDG = 0,
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}
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unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
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#[inline(always)]
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fn number(self) -> u16 {
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self as u16
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}
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}
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declare!(ADC);
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declare!(CAN1_RX0);
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declare!(CAN1_RX1);
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declare!(CAN1_SCE);
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declare!(CAN1_TX);
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declare!(CAN2_RX0);
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declare!(CAN2_RX1);
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declare!(CAN2_SCE);
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declare!(CAN2_TX);
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declare!(DFSDM1_FLT0);
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declare!(DFSDM1_FLT1);
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declare!(DMA1_Stream0);
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declare!(DMA1_Stream1);
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declare!(DMA1_Stream2);
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declare!(DMA1_Stream3);
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declare!(DMA1_Stream4);
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declare!(DMA1_Stream5);
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declare!(DMA1_Stream6);
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declare!(DMA1_Stream7);
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declare!(DMA2_Stream0);
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declare!(DMA2_Stream1);
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declare!(DMA2_Stream2);
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declare!(DMA2_Stream3);
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declare!(DMA2_Stream4);
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declare!(DMA2_Stream5);
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declare!(DMA2_Stream6);
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declare!(DMA2_Stream7);
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declare!(EXTI0);
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declare!(EXTI1);
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declare!(EXTI15_10);
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declare!(EXTI2);
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declare!(EXTI3);
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declare!(EXTI4);
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declare!(EXTI9_5);
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declare!(FLASH);
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declare!(FMPI2C1_ER);
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declare!(FMPI2C1_EV);
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declare!(FPU);
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declare!(I2C1_ER);
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declare!(I2C1_EV);
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declare!(I2C2_ER);
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declare!(I2C2_EV);
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declare!(I2C3_ER);
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declare!(I2C3_EV);
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declare!(OTG_FS);
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declare!(OTG_FS_WKUP);
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declare!(PVD);
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declare!(QUADSPI);
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declare!(RCC);
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declare!(RNG);
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declare!(RTC_Alarm);
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declare!(RTC_WKUP);
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declare!(SDIO);
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declare!(SPI1);
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declare!(SPI2);
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declare!(SPI3);
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declare!(SPI4);
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declare!(SPI5);
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declare!(TAMP_STAMP);
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declare!(TIM1_BRK_TIM9);
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declare!(TIM1_CC);
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declare!(TIM1_TRG_COM_TIM11);
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declare!(TIM1_UP_TIM10);
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declare!(TIM2);
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declare!(TIM3);
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declare!(TIM4);
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declare!(TIM5);
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declare!(TIM6);
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declare!(TIM7);
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declare!(TIM8_BRK_TIM12);
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declare!(TIM8_CC);
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declare!(TIM8_TRG_COM_TIM14);
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declare!(TIM8_UP_TIM13);
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declare!(USART1);
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declare!(USART2);
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declare!(USART3);
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declare!(USART6);
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declare!(WWDG);
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}
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mod interrupt_vector {
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extern "C" {
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fn ADC();
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fn CAN1_RX0();
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fn CAN1_RX1();
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fn CAN1_SCE();
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fn CAN1_TX();
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fn CAN2_RX0();
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fn CAN2_RX1();
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fn CAN2_SCE();
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fn CAN2_TX();
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fn DFSDM1_FLT0();
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fn DFSDM1_FLT1();
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fn DMA1_Stream0();
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fn DMA1_Stream1();
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fn DMA1_Stream2();
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fn DMA1_Stream3();
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fn DMA1_Stream4();
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fn DMA1_Stream5();
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fn DMA1_Stream6();
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fn DMA1_Stream7();
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fn DMA2_Stream0();
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fn DMA2_Stream1();
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fn DMA2_Stream2();
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fn DMA2_Stream3();
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fn DMA2_Stream4();
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fn DMA2_Stream5();
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fn DMA2_Stream6();
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fn DMA2_Stream7();
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fn EXTI0();
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fn EXTI1();
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fn EXTI15_10();
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fn EXTI2();
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fn EXTI3();
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fn EXTI4();
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fn EXTI9_5();
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fn FLASH();
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fn FMPI2C1_ER();
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fn FMPI2C1_EV();
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fn FPU();
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fn I2C1_ER();
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fn I2C1_EV();
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fn I2C2_ER();
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fn I2C2_EV();
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fn I2C3_ER();
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fn I2C3_EV();
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fn OTG_FS();
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fn OTG_FS_WKUP();
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fn PVD();
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fn QUADSPI();
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fn RCC();
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fn RNG();
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fn RTC_Alarm();
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fn RTC_WKUP();
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fn SDIO();
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fn SPI1();
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fn SPI2();
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fn SPI3();
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fn SPI4();
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fn SPI5();
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fn TAMP_STAMP();
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fn TIM1_BRK_TIM9();
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fn TIM1_CC();
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fn TIM1_TRG_COM_TIM11();
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fn TIM1_UP_TIM10();
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fn TIM2();
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fn TIM3();
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fn TIM4();
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fn TIM5();
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fn TIM6();
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fn TIM7();
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fn TIM8_BRK_TIM12();
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fn TIM8_CC();
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fn TIM8_TRG_COM_TIM14();
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fn TIM8_UP_TIM13();
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fn USART1();
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fn USART2();
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fn USART3();
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fn USART6();
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fn WWDG();
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}
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pub union Vector {
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_handler: unsafe extern "C" fn(),
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_reserved: u32,
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}
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#[link_section = ".vector_table.interrupts"]
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#[no_mangle]
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pub static __INTERRUPTS: [Vector; 97] = [
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Vector { _handler: WWDG },
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Vector { _handler: PVD },
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Vector {
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_handler: TAMP_STAMP,
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},
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Vector { _handler: RTC_WKUP },
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Vector { _handler: FLASH },
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Vector { _handler: RCC },
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Vector { _handler: EXTI0 },
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Vector { _handler: EXTI1 },
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Vector { _handler: EXTI2 },
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Vector { _handler: EXTI3 },
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Vector { _handler: EXTI4 },
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Vector {
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_handler: DMA1_Stream0,
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},
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Vector {
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_handler: DMA1_Stream1,
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},
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Vector {
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_handler: DMA1_Stream2,
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},
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Vector {
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_handler: DMA1_Stream3,
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},
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Vector {
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_handler: DMA1_Stream4,
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},
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Vector {
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_handler: DMA1_Stream5,
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},
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Vector {
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_handler: DMA1_Stream6,
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},
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Vector { _handler: ADC },
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Vector { _handler: CAN1_TX },
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Vector { _handler: CAN1_RX0 },
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Vector { _handler: CAN1_RX1 },
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Vector { _handler: CAN1_SCE },
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Vector { _handler: EXTI9_5 },
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Vector {
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_handler: TIM1_BRK_TIM9,
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},
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Vector {
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_handler: TIM1_UP_TIM10,
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},
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Vector {
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_handler: TIM1_TRG_COM_TIM11,
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},
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Vector { _handler: TIM1_CC },
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Vector { _handler: TIM2 },
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Vector { _handler: TIM3 },
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Vector { _handler: TIM4 },
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Vector { _handler: I2C1_EV },
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Vector { _handler: I2C1_ER },
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Vector { _handler: I2C2_EV },
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Vector { _handler: I2C2_ER },
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Vector { _handler: SPI1 },
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Vector { _handler: SPI2 },
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Vector { _handler: USART1 },
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Vector { _handler: USART2 },
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Vector { _handler: USART3 },
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Vector {
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_handler: EXTI15_10,
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},
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Vector {
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_handler: RTC_Alarm,
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},
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Vector {
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_handler: OTG_FS_WKUP,
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},
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Vector {
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_handler: TIM8_BRK_TIM12,
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},
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Vector {
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_handler: TIM8_UP_TIM13,
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},
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Vector {
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_handler: TIM8_TRG_COM_TIM14,
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},
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Vector { _handler: TIM8_CC },
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Vector {
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_handler: DMA1_Stream7,
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},
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Vector { _reserved: 0 },
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Vector { _handler: SDIO },
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Vector { _handler: TIM5 },
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Vector { _handler: SPI3 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _handler: TIM6 },
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Vector { _handler: TIM7 },
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Vector {
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_handler: DMA2_Stream0,
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},
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Vector {
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_handler: DMA2_Stream1,
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},
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Vector {
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_handler: DMA2_Stream2,
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},
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Vector {
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_handler: DMA2_Stream3,
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},
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Vector {
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_handler: DMA2_Stream4,
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},
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Vector {
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_handler: DFSDM1_FLT0,
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},
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Vector {
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_handler: DFSDM1_FLT1,
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},
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Vector { _handler: CAN2_TX },
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Vector { _handler: CAN2_RX0 },
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Vector { _handler: CAN2_RX1 },
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Vector { _handler: CAN2_SCE },
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Vector { _handler: OTG_FS },
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Vector {
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_handler: DMA2_Stream5,
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},
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Vector {
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_handler: DMA2_Stream6,
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},
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Vector {
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_handler: DMA2_Stream7,
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},
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Vector { _handler: USART6 },
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Vector { _handler: I2C3_EV },
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Vector { _handler: I2C3_ER },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _handler: RNG },
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Vector { _handler: FPU },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _handler: SPI4 },
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Vector { _handler: SPI5 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector { _handler: QUADSPI },
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Vector { _reserved: 0 },
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Vector { _reserved: 0 },
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Vector {
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_handler: FMPI2C1_EV,
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},
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Vector {
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_handler: FMPI2C1_ER,
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},
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];
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}
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impl_gpio_pin!(PA0, 0, 0, EXTI0);
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impl_gpio_pin!(PA1, 0, 1, EXTI1);
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impl_gpio_pin!(PA2, 0, 2, EXTI2);
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