stm32: codegen interrupts
This commit is contained in:
Dario Nieuwenhuis
@ -46,17 +46,17 @@ macro_rules! peripherals {
|
||||
impl Peripherals {
|
||||
///Returns all the peripherals *once*
|
||||
#[inline]
|
||||
pub fn take() -> Option<Self> {
|
||||
pub(crate) fn take() -> Self {
|
||||
|
||||
#[no_mangle]
|
||||
static mut _EMBASSY_DEVICE_PERIPHERALS: bool = false;
|
||||
|
||||
cortex_m::interrupt::free(|_| {
|
||||
if unsafe { _EMBASSY_DEVICE_PERIPHERALS } {
|
||||
None
|
||||
cortex_m::interrupt::free(|_| unsafe {
|
||||
if _EMBASSY_DEVICE_PERIPHERALS {
|
||||
panic!("init called twice")
|
||||
} else {
|
||||
unsafe { _EMBASSY_DEVICE_PERIPHERALS = true };
|
||||
Some(unsafe { <Self as embassy::util::Steal>::steal() })
|
||||
_EMBASSY_DEVICE_PERIPHERALS = true;
|
||||
<Self as embassy::util::Steal>::steal()
|
||||
}
|
||||
})
|
||||
}
|
||||
|
||||
@ -3,9 +3,13 @@
|
||||
extern crate proc_macro;
|
||||
|
||||
use darling::FromMeta;
|
||||
use proc_macro::{Span, TokenStream};
|
||||
use proc_macro::TokenStream;
|
||||
use proc_macro2::Span;
|
||||
use quote::{format_ident, quote};
|
||||
use std::iter;
|
||||
use syn::spanned::Spanned;
|
||||
use syn::{parse, Type, Visibility};
|
||||
use syn::{ItemFn, ReturnType};
|
||||
|
||||
mod path;
|
||||
|
||||
@ -58,10 +62,9 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream {
|
||||
fail = true;
|
||||
}
|
||||
if pool_size < 1 {
|
||||
Span::call_site()
|
||||
.error("pool_size must be 1 or greater")
|
||||
.emit();
|
||||
fail = true
|
||||
return parse::Error::new(Span::call_site(), "pool_size must be 1 or greater")
|
||||
.to_compile_error()
|
||||
.into();
|
||||
}
|
||||
|
||||
let mut arg_names: syn::punctuated::Punctuated<syn::Ident, syn::Token![,]> =
|
||||
@ -120,6 +123,66 @@ pub fn task(args: TokenStream, item: TokenStream) -> TokenStream {
|
||||
result.into()
|
||||
}
|
||||
|
||||
#[proc_macro_attribute]
|
||||
pub fn interrupt(args: TokenStream, input: TokenStream) -> TokenStream {
|
||||
let mut f: ItemFn = syn::parse(input).expect("`#[interrupt]` must be applied to a function");
|
||||
|
||||
if !args.is_empty() {
|
||||
return parse::Error::new(Span::call_site(), "This attribute accepts no arguments")
|
||||
.to_compile_error()
|
||||
.into();
|
||||
}
|
||||
|
||||
let fspan = f.span();
|
||||
let ident = f.sig.ident.clone();
|
||||
let ident_s = ident.to_string();
|
||||
|
||||
// XXX should we blacklist other attributes?
|
||||
|
||||
let valid_signature = f.sig.constness.is_none()
|
||||
&& f.vis == Visibility::Inherited
|
||||
&& f.sig.abi.is_none()
|
||||
&& f.sig.inputs.is_empty()
|
||||
&& f.sig.generics.params.is_empty()
|
||||
&& f.sig.generics.where_clause.is_none()
|
||||
&& f.sig.variadic.is_none()
|
||||
&& match f.sig.output {
|
||||
ReturnType::Default => true,
|
||||
ReturnType::Type(_, ref ty) => match **ty {
|
||||
Type::Tuple(ref tuple) => tuple.elems.is_empty(),
|
||||
Type::Never(..) => true,
|
||||
_ => false,
|
||||
},
|
||||
};
|
||||
|
||||
if !valid_signature {
|
||||
return parse::Error::new(
|
||||
fspan,
|
||||
"`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`",
|
||||
)
|
||||
.to_compile_error()
|
||||
.into();
|
||||
}
|
||||
|
||||
f.block.stmts = iter::once(
|
||||
syn::parse2(quote! {{
|
||||
// Check that this interrupt actually exists
|
||||
let __irq_exists_check: interrupt::#ident;
|
||||
}})
|
||||
.unwrap(),
|
||||
)
|
||||
.chain(f.block.stmts)
|
||||
.collect();
|
||||
|
||||
quote!(
|
||||
#[doc(hidden)]
|
||||
#[export_name = #ident_s]
|
||||
#[allow(non_snake_case)]
|
||||
#f
|
||||
)
|
||||
.into()
|
||||
}
|
||||
|
||||
#[proc_macro]
|
||||
pub fn interrupt_declare(item: TokenStream) -> TokenStream {
|
||||
let name = syn::parse_macro_input!(item as syn::Ident);
|
||||
|
||||
@ -20,7 +20,7 @@ embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-
|
||||
embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
|
||||
embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"] }
|
||||
embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
|
||||
stm32f4 = { version = "0.13", features = ["stm32f429", "rt"] }
|
||||
stm32f4 = { version = "0.13", features = ["stm32f429"] }
|
||||
|
||||
defmt = "0.2.0"
|
||||
defmt-rtt = "0.2.0"
|
||||
|
||||
@ -37,7 +37,8 @@ fn main() -> ! {
|
||||
w
|
||||
});
|
||||
|
||||
let p = embassy_stm32::Peripherals::take().unwrap();
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let mut led = Output::new(p.PB7, Level::High);
|
||||
|
||||
loop {
|
||||
|
||||
@ -37,7 +37,8 @@ fn main() -> ! {
|
||||
w
|
||||
});
|
||||
|
||||
let p = embassy_stm32::Peripherals::take().unwrap();
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let button = Input::new(p.PC13, Pull::Down);
|
||||
let mut led1 = Output::new(p.PB0, Level::High);
|
||||
let _led2 = Output::new(p.PB7, Level::High);
|
||||
|
||||
@ -16,12 +16,12 @@ use embassy_traits::gpio::{WaitForFallingEdge, WaitForRisingEdge};
|
||||
use example_common::*;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use pac::{interrupt, NVIC};
|
||||
use stm32f4::stm32f429 as pac;
|
||||
|
||||
#[embassy::task]
|
||||
async fn main_task() {
|
||||
let p = embassy_stm32::Peripherals::take().unwrap();
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let button = Input::new(p.PC13, Pull::Down);
|
||||
let mut button = ExtiInput::new(button, p.EXTI13);
|
||||
|
||||
@ -74,56 +74,9 @@ fn main() -> ! {
|
||||
|
||||
unsafe { embassy::time::set_clock(&ZeroClock) };
|
||||
|
||||
unsafe {
|
||||
NVIC::unmask(interrupt::EXTI0);
|
||||
NVIC::unmask(interrupt::EXTI1);
|
||||
NVIC::unmask(interrupt::EXTI2);
|
||||
NVIC::unmask(interrupt::EXTI3);
|
||||
NVIC::unmask(interrupt::EXTI4);
|
||||
NVIC::unmask(interrupt::EXTI9_5);
|
||||
NVIC::unmask(interrupt::EXTI15_10);
|
||||
}
|
||||
|
||||
let executor = EXECUTOR.put(Executor::new());
|
||||
|
||||
executor.run(|spawner| {
|
||||
unwrap!(spawner.spawn(main_task()));
|
||||
})
|
||||
}
|
||||
|
||||
// TODO for now irq handling is done by user code using the old pac, until we figure out how interrupts work in the metapac
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI0() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI1() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI2() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI3() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI4() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI9_5() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
#[interrupt]
|
||||
unsafe fn EXTI15_10() {
|
||||
exti::on_irq()
|
||||
}
|
||||
|
||||
@ -15,12 +15,11 @@ use embassy_stm32::usart::{Config, Uart};
|
||||
use example_common::*;
|
||||
|
||||
use cortex_m_rt::entry;
|
||||
use pac::{interrupt, NVIC};
|
||||
use stm32f4::stm32f429 as pac;
|
||||
|
||||
#[embassy::task]
|
||||
async fn main_task() {
|
||||
let p = embassy_stm32::Peripherals::take().unwrap();
|
||||
let p = embassy_stm32::init(Default::default());
|
||||
|
||||
let config = Config::default();
|
||||
let usart = Uart::new(p.USART3, p.PD9, p.PD8, NoPin, NoPin, config);
|
||||
@ -61,10 +60,13 @@ fn main() -> ! {
|
||||
w
|
||||
});
|
||||
pp.RCC.apb2enr.modify(|_, w| {
|
||||
w.usart3en().enabled();
|
||||
w.syscfgen().enabled();
|
||||
w
|
||||
});
|
||||
pp.RCC.apb1enr.modify(|_, w| {
|
||||
w.usart3en().enabled();
|
||||
w
|
||||
});
|
||||
|
||||
unsafe { embassy::time::set_clock(&ZeroClock) };
|
||||
|
||||
|
||||
@ -11,12 +11,15 @@ embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
|
||||
|
||||
defmt = { version = "0.2.0", optional = true }
|
||||
log = { version = "0.4.11", optional = true }
|
||||
cortex-m-rt = "0.6.13"
|
||||
cortex-m-rt = { version = "0.6.13", features = ["device"] }
|
||||
cortex-m = "0.7.1"
|
||||
embedded-hal = { version = "0.2.4" }
|
||||
futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
|
||||
stm32-metapac = { path = "../../stm32-metapac"}
|
||||
|
||||
[build-dependencies]
|
||||
regex = "1.4.6"
|
||||
|
||||
[features]
|
||||
defmt-trace = [ ]
|
||||
defmt-debug = [ ]
|
||||
|
||||
34
embassy-stm32/build.rs
Normal file
34
embassy-stm32/build.rs
Normal file
@ -0,0 +1,34 @@
|
||||
use regex::Regex;
|
||||
use std::fmt::Write as _;
|
||||
use std::fs::File;
|
||||
use std::io::Write;
|
||||
use std::path::PathBuf;
|
||||
use std::{env, fs};
|
||||
|
||||
fn main() {
|
||||
let chip = env::vars_os()
|
||||
.map(|(a, _)| a.to_string_lossy().to_string())
|
||||
.find(|x| x.starts_with("CARGO_FEATURE_STM32"))
|
||||
.expect("No stm32xx Cargo feature enabled")
|
||||
.strip_prefix("CARGO_FEATURE_")
|
||||
.unwrap()
|
||||
.to_ascii_lowercase();
|
||||
|
||||
let mut device_x = String::new();
|
||||
|
||||
let chip_rs = fs::read_to_string(format!("src/chip/{}.rs", chip)).unwrap();
|
||||
let re = Regex::new("declare!\\(([a-zA-Z0-9_]+)\\)").unwrap();
|
||||
for c in re.captures_iter(&chip_rs) {
|
||||
let name = c.get(1).unwrap().as_str();
|
||||
write!(&mut device_x, "PROVIDE({} = DefaultHandler);\n", name).unwrap();
|
||||
}
|
||||
|
||||
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
|
||||
File::create(out.join("device.x"))
|
||||
.unwrap()
|
||||
.write_all(device_x.as_bytes())
|
||||
.unwrap();
|
||||
println!("cargo:rustc-link-search={}", out.display());
|
||||
println!("cargo:rerun-if-changed=src/chip/{}.rs", chip);
|
||||
println!("cargo:rerun-if-changed=build.rs");
|
||||
}
|
||||
@ -90,7 +90,7 @@ for chip in chips.values():
|
||||
if 'block' not in peri:
|
||||
continue
|
||||
|
||||
if peri['block'] == 'usart_v1/USART':
|
||||
if peri['block'] in ('usart_v1/USART', 'usart_v1/UART'):
|
||||
impls.append(f'impl_usart!({name}, 0x{peri["address"]:x});')
|
||||
for pin, funcs in af.items():
|
||||
if pin in pins:
|
||||
@ -108,23 +108,67 @@ for chip in chips.values():
|
||||
if peri['block'] == 'rng_v1/RNG':
|
||||
impls.append(f'impl_rng!(0x{peri["address"]:x});')
|
||||
|
||||
with open(f'src/chip/{chip["name"]}.rs', 'w') as f:
|
||||
# TODO uart etc
|
||||
# TODO import the right GPIO AF map mod
|
||||
# TODO impl traits for the periperals
|
||||
irq_variants = []
|
||||
irq_vectors = []
|
||||
irq_fns = []
|
||||
irq_declares = []
|
||||
|
||||
irqs = {num: name for name, num in chip['interrupts'].items()}
|
||||
irq_count = max(irqs.keys()) + 1
|
||||
for num, name in irqs.items():
|
||||
irq_variants.append(f'{name} = {num},')
|
||||
irq_fns.append(f'fn {name}();')
|
||||
irq_declares.append(f'declare!({name});')
|
||||
for num in range(irq_count):
|
||||
if name := irqs.get(num):
|
||||
irq_vectors.append(f'Vector {{ _handler: {name} }},')
|
||||
else:
|
||||
irq_vectors.append(f'Vector {{ _reserved: 0 }},')
|
||||
|
||||
with open(f'src/chip/{chip["name"]}.rs', 'w') as f:
|
||||
f.write(f"""
|
||||
use embassy_extras::peripherals;
|
||||
peripherals!({','.join(peripherals)});
|
||||
pub const GPIO_BASE: usize = 0x{gpio_base:x};
|
||||
pub const GPIO_STRIDE: usize = 0x{gpio_stride:x};
|
||||
|
||||
pub mod interrupt {{
|
||||
pub use cortex_m::interrupt::{{CriticalSection, Mutex}};
|
||||
pub use embassy::interrupt::{{declare, take, Interrupt}};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {{
|
||||
{''.join(irq_variants)}
|
||||
}}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {{
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {{
|
||||
self as u16
|
||||
}}
|
||||
}}
|
||||
|
||||
{''.join(irq_declares)}
|
||||
}}
|
||||
mod interrupt_vector {{
|
||||
extern "C" {{
|
||||
{''.join(irq_fns)}
|
||||
}}
|
||||
pub union Vector {{
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; {irq_count}] = [
|
||||
{''.join(irq_vectors)}
|
||||
];
|
||||
}}
|
||||
""")
|
||||
for i in impls:
|
||||
f.write(i)
|
||||
|
||||
|
||||
# TODO generate GPIO AF map mods
|
||||
|
||||
|
||||
# format
|
||||
os.system('rustfmt src/chip/*')
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,335 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 85] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,410 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,410 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,410 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,410 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,410 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,419 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,336 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,336 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,336 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,336 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,327 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -10,6 +10,327 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
LPTIM1 = 97,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SPI1 = 35,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP = 25,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SPI1);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn LPTIM1();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SPI1();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 98] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector { _handler: TIM1_UP },
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,339 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 86] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -11,6 +11,424 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -11,6 +11,424 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -12,6 +12,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,427 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6 = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 97] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: TIM6 },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,488 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,413 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,413 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,413 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,413 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,422 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CRYP = 79,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FPU = 81,
|
||||
FSMC = 48,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CRYP);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FPU);
|
||||
declare!(FSMC);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CRYP();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FPU();
|
||||
fn FSMC();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 82] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FSMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _handler: CRYP },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,491 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
AES = 79,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(AES);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn AES();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: AES },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,491 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
AES = 79,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(AES);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn AES();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: AES },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -15,6 +15,491 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
AES = 79,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(AES);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn AES();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: AES },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,491 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
AES = 79,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(AES);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn AES();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: AES },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -16,6 +16,491 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
AES = 79,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
CAN3_RX0 = 75,
|
||||
CAN3_RX1 = 76,
|
||||
CAN3_SCE = 77,
|
||||
CAN3_TX = 74,
|
||||
DFSDM1_FLT0 = 61,
|
||||
DFSDM1_FLT1 = 62,
|
||||
DFSDM2_FLT0 = 98,
|
||||
DFSDM2_FLT1 = 99,
|
||||
DFSDM2_FLT2 = 100,
|
||||
DFSDM2_FLT3 = 101,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMPI2C1_ER = 96,
|
||||
FMPI2C1_EV = 95,
|
||||
FPU = 81,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LPTIM1 = 97,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
PVD = 1,
|
||||
QUADSPI = 92,
|
||||
RCC = 5,
|
||||
RNG = 80,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART10 = 89,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
UART9 = 88,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(AES);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(CAN3_RX0);
|
||||
declare!(CAN3_RX1);
|
||||
declare!(CAN3_SCE);
|
||||
declare!(CAN3_TX);
|
||||
declare!(DFSDM1_FLT0);
|
||||
declare!(DFSDM1_FLT1);
|
||||
declare!(DFSDM2_FLT0);
|
||||
declare!(DFSDM2_FLT1);
|
||||
declare!(DFSDM2_FLT2);
|
||||
declare!(DFSDM2_FLT3);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMPI2C1_ER);
|
||||
declare!(FMPI2C1_EV);
|
||||
declare!(FPU);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LPTIM1);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(QUADSPI);
|
||||
declare!(RCC);
|
||||
declare!(RNG);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART10);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(UART9);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn AES();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn CAN3_RX0();
|
||||
fn CAN3_RX1();
|
||||
fn CAN3_SCE();
|
||||
fn CAN3_TX();
|
||||
fn DFSDM1_FLT0();
|
||||
fn DFSDM1_FLT1();
|
||||
fn DFSDM2_FLT0();
|
||||
fn DFSDM2_FLT1();
|
||||
fn DFSDM2_FLT2();
|
||||
fn DFSDM2_FLT3();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMPI2C1_ER();
|
||||
fn FMPI2C1_EV();
|
||||
fn FPU();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LPTIM1();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn PVD();
|
||||
fn QUADSPI();
|
||||
fn RCC();
|
||||
fn RNG();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART10();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn UART9();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 102] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM1_FLT1,
|
||||
},
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector { _handler: CAN3_TX },
|
||||
Vector { _handler: CAN3_RX0 },
|
||||
Vector { _handler: CAN3_RX1 },
|
||||
Vector { _handler: CAN3_SCE },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: AES },
|
||||
Vector { _handler: RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: UART9 },
|
||||
Vector { _handler: UART10 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: QUADSPI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector {
|
||||
_handler: FMPI2C1_EV,
|
||||
},
|
||||
Vector {
|
||||
_handler: FMPI2C1_ER,
|
||||
},
|
||||
Vector { _handler: LPTIM1 },
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DFSDM2_FLT3,
|
||||
},
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,449 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
@ -18,6 +18,455 @@ peripherals!(
|
||||
);
|
||||
pub const GPIO_BASE: usize = 0x40020000;
|
||||
pub const GPIO_STRIDE: usize = 0x400;
|
||||
|
||||
pub mod interrupt {
|
||||
pub use cortex_m::interrupt::{CriticalSection, Mutex};
|
||||
pub use embassy::interrupt::{declare, take, Interrupt};
|
||||
pub use embassy_extras::interrupt::Priority4 as Priority;
|
||||
|
||||
#[derive(Copy, Clone, Debug, PartialEq, Eq)]
|
||||
#[allow(non_camel_case_types)]
|
||||
enum InterruptEnum {
|
||||
ADC = 18,
|
||||
CAN1_RX0 = 20,
|
||||
CAN1_RX1 = 21,
|
||||
CAN1_SCE = 22,
|
||||
CAN1_TX = 19,
|
||||
CAN2_RX0 = 64,
|
||||
CAN2_RX1 = 65,
|
||||
CAN2_SCE = 66,
|
||||
CAN2_TX = 63,
|
||||
DCMI = 78,
|
||||
DMA1_Stream0 = 11,
|
||||
DMA1_Stream1 = 12,
|
||||
DMA1_Stream2 = 13,
|
||||
DMA1_Stream3 = 14,
|
||||
DMA1_Stream4 = 15,
|
||||
DMA1_Stream5 = 16,
|
||||
DMA1_Stream6 = 17,
|
||||
DMA1_Stream7 = 47,
|
||||
DMA2D = 90,
|
||||
DMA2_Stream0 = 56,
|
||||
DMA2_Stream1 = 57,
|
||||
DMA2_Stream2 = 58,
|
||||
DMA2_Stream3 = 59,
|
||||
DMA2_Stream4 = 60,
|
||||
DMA2_Stream5 = 68,
|
||||
DMA2_Stream6 = 69,
|
||||
DMA2_Stream7 = 70,
|
||||
ETH = 61,
|
||||
ETH_WKUP = 62,
|
||||
EXTI0 = 6,
|
||||
EXTI1 = 7,
|
||||
EXTI15_10 = 40,
|
||||
EXTI2 = 8,
|
||||
EXTI3 = 9,
|
||||
EXTI4 = 10,
|
||||
EXTI9_5 = 23,
|
||||
FLASH = 4,
|
||||
FMC = 48,
|
||||
FPU = 81,
|
||||
HASH_RNG = 80,
|
||||
I2C1_ER = 32,
|
||||
I2C1_EV = 31,
|
||||
I2C2_ER = 34,
|
||||
I2C2_EV = 33,
|
||||
I2C3_ER = 73,
|
||||
I2C3_EV = 72,
|
||||
LTDC = 88,
|
||||
LTDC_ER = 89,
|
||||
OTG_FS = 67,
|
||||
OTG_FS_WKUP = 42,
|
||||
OTG_HS = 77,
|
||||
OTG_HS_EP1_IN = 75,
|
||||
OTG_HS_EP1_OUT = 74,
|
||||
OTG_HS_WKUP = 76,
|
||||
PVD = 1,
|
||||
RCC = 5,
|
||||
RTC_Alarm = 41,
|
||||
RTC_WKUP = 3,
|
||||
SAI1 = 87,
|
||||
SDIO = 49,
|
||||
SPI1 = 35,
|
||||
SPI2 = 36,
|
||||
SPI3 = 51,
|
||||
SPI4 = 84,
|
||||
SPI5 = 85,
|
||||
SPI6 = 86,
|
||||
TAMP_STAMP = 2,
|
||||
TIM1_BRK_TIM9 = 24,
|
||||
TIM1_CC = 27,
|
||||
TIM1_TRG_COM_TIM11 = 26,
|
||||
TIM1_UP_TIM10 = 25,
|
||||
TIM2 = 28,
|
||||
TIM3 = 29,
|
||||
TIM4 = 30,
|
||||
TIM5 = 50,
|
||||
TIM6_DAC = 54,
|
||||
TIM7 = 55,
|
||||
TIM8_BRK_TIM12 = 43,
|
||||
TIM8_CC = 46,
|
||||
TIM8_TRG_COM_TIM14 = 45,
|
||||
TIM8_UP_TIM13 = 44,
|
||||
UART4 = 52,
|
||||
UART5 = 53,
|
||||
UART7 = 82,
|
||||
UART8 = 83,
|
||||
USART1 = 37,
|
||||
USART2 = 38,
|
||||
USART3 = 39,
|
||||
USART6 = 71,
|
||||
WWDG = 0,
|
||||
}
|
||||
unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
|
||||
#[inline(always)]
|
||||
fn number(self) -> u16 {
|
||||
self as u16
|
||||
}
|
||||
}
|
||||
|
||||
declare!(ADC);
|
||||
declare!(CAN1_RX0);
|
||||
declare!(CAN1_RX1);
|
||||
declare!(CAN1_SCE);
|
||||
declare!(CAN1_TX);
|
||||
declare!(CAN2_RX0);
|
||||
declare!(CAN2_RX1);
|
||||
declare!(CAN2_SCE);
|
||||
declare!(CAN2_TX);
|
||||
declare!(DCMI);
|
||||
declare!(DMA1_Stream0);
|
||||
declare!(DMA1_Stream1);
|
||||
declare!(DMA1_Stream2);
|
||||
declare!(DMA1_Stream3);
|
||||
declare!(DMA1_Stream4);
|
||||
declare!(DMA1_Stream5);
|
||||
declare!(DMA1_Stream6);
|
||||
declare!(DMA1_Stream7);
|
||||
declare!(DMA2D);
|
||||
declare!(DMA2_Stream0);
|
||||
declare!(DMA2_Stream1);
|
||||
declare!(DMA2_Stream2);
|
||||
declare!(DMA2_Stream3);
|
||||
declare!(DMA2_Stream4);
|
||||
declare!(DMA2_Stream5);
|
||||
declare!(DMA2_Stream6);
|
||||
declare!(DMA2_Stream7);
|
||||
declare!(ETH);
|
||||
declare!(ETH_WKUP);
|
||||
declare!(EXTI0);
|
||||
declare!(EXTI1);
|
||||
declare!(EXTI15_10);
|
||||
declare!(EXTI2);
|
||||
declare!(EXTI3);
|
||||
declare!(EXTI4);
|
||||
declare!(EXTI9_5);
|
||||
declare!(FLASH);
|
||||
declare!(FMC);
|
||||
declare!(FPU);
|
||||
declare!(HASH_RNG);
|
||||
declare!(I2C1_ER);
|
||||
declare!(I2C1_EV);
|
||||
declare!(I2C2_ER);
|
||||
declare!(I2C2_EV);
|
||||
declare!(I2C3_ER);
|
||||
declare!(I2C3_EV);
|
||||
declare!(LTDC);
|
||||
declare!(LTDC_ER);
|
||||
declare!(OTG_FS);
|
||||
declare!(OTG_FS_WKUP);
|
||||
declare!(OTG_HS);
|
||||
declare!(OTG_HS_EP1_IN);
|
||||
declare!(OTG_HS_EP1_OUT);
|
||||
declare!(OTG_HS_WKUP);
|
||||
declare!(PVD);
|
||||
declare!(RCC);
|
||||
declare!(RTC_Alarm);
|
||||
declare!(RTC_WKUP);
|
||||
declare!(SAI1);
|
||||
declare!(SDIO);
|
||||
declare!(SPI1);
|
||||
declare!(SPI2);
|
||||
declare!(SPI3);
|
||||
declare!(SPI4);
|
||||
declare!(SPI5);
|
||||
declare!(SPI6);
|
||||
declare!(TAMP_STAMP);
|
||||
declare!(TIM1_BRK_TIM9);
|
||||
declare!(TIM1_CC);
|
||||
declare!(TIM1_TRG_COM_TIM11);
|
||||
declare!(TIM1_UP_TIM10);
|
||||
declare!(TIM2);
|
||||
declare!(TIM3);
|
||||
declare!(TIM4);
|
||||
declare!(TIM5);
|
||||
declare!(TIM6_DAC);
|
||||
declare!(TIM7);
|
||||
declare!(TIM8_BRK_TIM12);
|
||||
declare!(TIM8_CC);
|
||||
declare!(TIM8_TRG_COM_TIM14);
|
||||
declare!(TIM8_UP_TIM13);
|
||||
declare!(UART4);
|
||||
declare!(UART5);
|
||||
declare!(UART7);
|
||||
declare!(UART8);
|
||||
declare!(USART1);
|
||||
declare!(USART2);
|
||||
declare!(USART3);
|
||||
declare!(USART6);
|
||||
declare!(WWDG);
|
||||
}
|
||||
mod interrupt_vector {
|
||||
extern "C" {
|
||||
fn ADC();
|
||||
fn CAN1_RX0();
|
||||
fn CAN1_RX1();
|
||||
fn CAN1_SCE();
|
||||
fn CAN1_TX();
|
||||
fn CAN2_RX0();
|
||||
fn CAN2_RX1();
|
||||
fn CAN2_SCE();
|
||||
fn CAN2_TX();
|
||||
fn DCMI();
|
||||
fn DMA1_Stream0();
|
||||
fn DMA1_Stream1();
|
||||
fn DMA1_Stream2();
|
||||
fn DMA1_Stream3();
|
||||
fn DMA1_Stream4();
|
||||
fn DMA1_Stream5();
|
||||
fn DMA1_Stream6();
|
||||
fn DMA1_Stream7();
|
||||
fn DMA2D();
|
||||
fn DMA2_Stream0();
|
||||
fn DMA2_Stream1();
|
||||
fn DMA2_Stream2();
|
||||
fn DMA2_Stream3();
|
||||
fn DMA2_Stream4();
|
||||
fn DMA2_Stream5();
|
||||
fn DMA2_Stream6();
|
||||
fn DMA2_Stream7();
|
||||
fn ETH();
|
||||
fn ETH_WKUP();
|
||||
fn EXTI0();
|
||||
fn EXTI1();
|
||||
fn EXTI15_10();
|
||||
fn EXTI2();
|
||||
fn EXTI3();
|
||||
fn EXTI4();
|
||||
fn EXTI9_5();
|
||||
fn FLASH();
|
||||
fn FMC();
|
||||
fn FPU();
|
||||
fn HASH_RNG();
|
||||
fn I2C1_ER();
|
||||
fn I2C1_EV();
|
||||
fn I2C2_ER();
|
||||
fn I2C2_EV();
|
||||
fn I2C3_ER();
|
||||
fn I2C3_EV();
|
||||
fn LTDC();
|
||||
fn LTDC_ER();
|
||||
fn OTG_FS();
|
||||
fn OTG_FS_WKUP();
|
||||
fn OTG_HS();
|
||||
fn OTG_HS_EP1_IN();
|
||||
fn OTG_HS_EP1_OUT();
|
||||
fn OTG_HS_WKUP();
|
||||
fn PVD();
|
||||
fn RCC();
|
||||
fn RTC_Alarm();
|
||||
fn RTC_WKUP();
|
||||
fn SAI1();
|
||||
fn SDIO();
|
||||
fn SPI1();
|
||||
fn SPI2();
|
||||
fn SPI3();
|
||||
fn SPI4();
|
||||
fn SPI5();
|
||||
fn SPI6();
|
||||
fn TAMP_STAMP();
|
||||
fn TIM1_BRK_TIM9();
|
||||
fn TIM1_CC();
|
||||
fn TIM1_TRG_COM_TIM11();
|
||||
fn TIM1_UP_TIM10();
|
||||
fn TIM2();
|
||||
fn TIM3();
|
||||
fn TIM4();
|
||||
fn TIM5();
|
||||
fn TIM6_DAC();
|
||||
fn TIM7();
|
||||
fn TIM8_BRK_TIM12();
|
||||
fn TIM8_CC();
|
||||
fn TIM8_TRG_COM_TIM14();
|
||||
fn TIM8_UP_TIM13();
|
||||
fn UART4();
|
||||
fn UART5();
|
||||
fn UART7();
|
||||
fn UART8();
|
||||
fn USART1();
|
||||
fn USART2();
|
||||
fn USART3();
|
||||
fn USART6();
|
||||
fn WWDG();
|
||||
}
|
||||
pub union Vector {
|
||||
_handler: unsafe extern "C" fn(),
|
||||
_reserved: u32,
|
||||
}
|
||||
#[link_section = ".vector_table.interrupts"]
|
||||
#[no_mangle]
|
||||
pub static __INTERRUPTS: [Vector; 91] = [
|
||||
Vector { _handler: WWDG },
|
||||
Vector { _handler: PVD },
|
||||
Vector {
|
||||
_handler: TAMP_STAMP,
|
||||
},
|
||||
Vector { _handler: RTC_WKUP },
|
||||
Vector { _handler: FLASH },
|
||||
Vector { _handler: RCC },
|
||||
Vector { _handler: EXTI0 },
|
||||
Vector { _handler: EXTI1 },
|
||||
Vector { _handler: EXTI2 },
|
||||
Vector { _handler: EXTI3 },
|
||||
Vector { _handler: EXTI4 },
|
||||
Vector {
|
||||
_handler: DMA1_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream4,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA1_Stream6,
|
||||
},
|
||||
Vector { _handler: ADC },
|
||||
Vector { _handler: CAN1_TX },
|
||||
Vector { _handler: CAN1_RX0 },
|
||||
Vector { _handler: CAN1_RX1 },
|
||||
Vector { _handler: CAN1_SCE },
|
||||
Vector { _handler: EXTI9_5 },
|
||||
Vector {
|
||||
_handler: TIM1_BRK_TIM9,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_UP_TIM10,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM1_TRG_COM_TIM11,
|
||||
},
|
||||
Vector { _handler: TIM1_CC },
|
||||
Vector { _handler: TIM2 },
|
||||
Vector { _handler: TIM3 },
|
||||
Vector { _handler: TIM4 },
|
||||
Vector { _handler: I2C1_EV },
|
||||
Vector { _handler: I2C1_ER },
|
||||
Vector { _handler: I2C2_EV },
|
||||
Vector { _handler: I2C2_ER },
|
||||
Vector { _handler: SPI1 },
|
||||
Vector { _handler: SPI2 },
|
||||
Vector { _handler: USART1 },
|
||||
Vector { _handler: USART2 },
|
||||
Vector { _handler: USART3 },
|
||||
Vector {
|
||||
_handler: EXTI15_10,
|
||||
},
|
||||
Vector {
|
||||
_handler: RTC_Alarm,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_FS_WKUP,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_BRK_TIM12,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_UP_TIM13,
|
||||
},
|
||||
Vector {
|
||||
_handler: TIM8_TRG_COM_TIM14,
|
||||
},
|
||||
Vector { _handler: TIM8_CC },
|
||||
Vector {
|
||||
_handler: DMA1_Stream7,
|
||||
},
|
||||
Vector { _handler: FMC },
|
||||
Vector { _handler: SDIO },
|
||||
Vector { _handler: TIM5 },
|
||||
Vector { _handler: SPI3 },
|
||||
Vector { _handler: UART4 },
|
||||
Vector { _handler: UART5 },
|
||||
Vector { _handler: TIM6_DAC },
|
||||
Vector { _handler: TIM7 },
|
||||
Vector {
|
||||
_handler: DMA2_Stream0,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream1,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream2,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream3,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream4,
|
||||
},
|
||||
Vector { _handler: ETH },
|
||||
Vector { _handler: ETH_WKUP },
|
||||
Vector { _handler: CAN2_TX },
|
||||
Vector { _handler: CAN2_RX0 },
|
||||
Vector { _handler: CAN2_RX1 },
|
||||
Vector { _handler: CAN2_SCE },
|
||||
Vector { _handler: OTG_FS },
|
||||
Vector {
|
||||
_handler: DMA2_Stream5,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream6,
|
||||
},
|
||||
Vector {
|
||||
_handler: DMA2_Stream7,
|
||||
},
|
||||
Vector { _handler: USART6 },
|
||||
Vector { _handler: I2C3_EV },
|
||||
Vector { _handler: I2C3_ER },
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_OUT,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_EP1_IN,
|
||||
},
|
||||
Vector {
|
||||
_handler: OTG_HS_WKUP,
|
||||
},
|
||||
Vector { _handler: OTG_HS },
|
||||
Vector { _handler: DCMI },
|
||||
Vector { _reserved: 0 },
|
||||
Vector { _handler: HASH_RNG },
|
||||
Vector { _handler: FPU },
|
||||
Vector { _handler: UART7 },
|
||||
Vector { _handler: UART8 },
|
||||
Vector { _handler: SPI4 },
|
||||
Vector { _handler: SPI5 },
|
||||
Vector { _handler: SPI6 },
|
||||
Vector { _handler: SAI1 },
|
||||
Vector { _handler: LTDC },
|
||||
Vector { _handler: LTDC_ER },
|
||||
Vector { _handler: DMA2D },
|
||||
];
|
||||
}
|
||||
impl_gpio_pin!(PA0, 0, 0, EXTI0);
|
||||
impl_gpio_pin!(PA1, 0, 1, EXTI1);
|
||||
impl_gpio_pin!(PA2, 0, 2, EXTI2);
|
||||
|
||||
Some files were not shown because too many files have changed in this diff Show More
Reference in New Issue
Block a user