stm32h7/rcc: remove unneeded DMA enable settings.
These are automatically enabled by dma::init().
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parent
5d2f40b337
commit
89b009b11d
@ -72,8 +72,6 @@ pub struct Config {
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pub pll1: PllConfig,
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pub pll2: PllConfig,
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pub pll3: PllConfig,
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pub enable_dma1: bool,
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pub enable_dma2: bool,
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}
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pub struct Rcc<'d> {
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@ -331,14 +329,6 @@ impl<'d> Rcc<'d> {
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});
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while !SYSCFG.cccsr().read().ready() {}
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if self.config.enable_dma1 {
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RCC.ahb1enr().modify(|w| w.set_dma1en(true));
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}
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if self.config.enable_dma2 {
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RCC.ahb1enr().modify(|w| w.set_dma2en(true));
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}
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CoreClocks {
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hclk: Hertz(rcc_hclk),
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pclk1: Hertz(rcc_pclk1),
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@ -34,8 +34,6 @@ pub fn config() -> Config {
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config.rcc.sys_ck = Some(400.mhz().into());
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config.rcc.hclk = Some(400.mhz().into());
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config.rcc.pll1.q_ck = Some(100.mhz().into());
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config.rcc.enable_dma1 = true;
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config.rcc.enable_dma2 = true;
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config.rcc.pclk1 = Some(100.mhz().into());
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config.rcc.pclk2 = Some(100.mhz().into());
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config.rcc.pclk3 = Some(100.mhz().into());
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@ -23,6 +23,5 @@ pub fn config() -> Config {
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let mut config = Config::default();
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config.rcc.sys_ck = Some(400.mhz().into());
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config.rcc.pll1.q_ck = Some(100.mhz().into());
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config.rcc.enable_dma1 = true;
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config
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}
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