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Make interrupt module more standard.

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- Move typelevel interrupts to a special-purpose mod: `embassy_xx::interrupt::typelevel`.
- Reexport the PAC interrupt enum in `embassy_xx::interrupt`.

This has a few advantages:
- The `embassy_xx::interrupt` module is now more "standard".
  - It works with `cortex-m` functions for manipulating interrupts, for example.
  - It works with RTIC.
- the interrupt enum allows holding value that can be "any interrupt at runtime", this can't be done with typelevel irqs.
- When "const-generics on enums" is stable, we can remove the typelevel interrupts without disruptive changes to `embassy_xx::interrupt`.
This commit is contained in:
Dario Nieuwenhuis 2023-06-08 16:08:40 +02:00
parent 87ad66f2b4
commit 921780e6bf
72 changed files with 845 additions and 930 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

211
embassy-cortex-m/src/interrupt.rs
View File

@ -2,120 +2,207 @@
use core::mem;
use core::sync::atomic::{compiler_fence, Ordering};
use cortex_m::interrupt::InterruptNumber;
use cortex_m::peripheral::NVIC;
/// Do not use. Used for macros and HALs only. Not covered by semver guarantees.
#[doc(hidden)]
pub mod _export {
pub use atomic_polyfill as atomic;
pub use embassy_macros::{cortex_m_interrupt as interrupt, cortex_m_interrupt_declare as declare};
}
/// Generate a standard `mod interrupt` for a HAL.
#[macro_export]
macro_rules! interrupt_mod {
($($irqs:ident),* $(,)?) => {
pub use cortex_m_rt::interrupt;
/// Interrupt handler trait.
///
/// Drivers that need to handle interrupts implement this trait.
/// The user must ensure `on_interrupt()` is called every time the interrupt fires.
/// Drivers must use use [`Binding`] to assert at compile time that the user has done so.
pub trait Handler<I: Interrupt> {
/// Interrupt handler function.
///
/// Must be called every time the `I` interrupt fires, synchronously from
/// the interrupt handler context.
///
/// # Safety
///
/// This function must ONLY be called from the interrupt handler for `I`.
unsafe fn on_interrupt();
}
/// Interrupt definitions.
pub mod interrupt {
pub use embassy_cortex_m::interrupt::{InterruptExt, Priority};
pub use crate::pac::interrupt::*;
pub use crate::pac::Interrupt;
/// Compile-time assertion that an interrupt has been bound to a handler.
///
/// For the vast majority of cases, you should use the `bind_interrupts!`
/// macro instead of writing `unsafe impl`s of this trait.
///
/// # Safety
///
/// By implementing this trait, you are asserting that you have arranged for `H::on_interrupt()`
/// to be called every time the `I` interrupt fires.
///
/// This allows drivers to check bindings at compile-time.
pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {}
/// Type-level interrupt infrastructure.
///
/// This module contains one *type* per interrupt. This is used for checking at compile time that
/// the interrupts are correctly bound to HAL drivers.
///
/// As an end user, you shouldn't need to use this module directly. Use the [`crate::bind_interrupts!`] macro
/// to bind interrupts, and the [`crate::interrupt`] module to manually register interrupt handlers and manipulate
/// interrupts directly (pending/unpending, enabling/disabling, setting the priority, etc...)
pub mod typelevel {
use super::InterruptExt;
#[derive(Clone, Copy)]
pub(crate) struct NrWrap(pub(crate) u16);
unsafe impl cortex_m::interrupt::InterruptNumber for NrWrap {
fn number(self) -> u16 {
self.0
}
mod sealed {
pub trait Interrupt {}
}
/// Type-level interrupt.
///
/// This trait is implemented for all typelevel interrupt types in this module.
pub trait Interrupt: sealed::Interrupt {
/// Interrupt enum variant.
///
/// This allows going from typelevel interrupts (one type per interrupt) to
/// non-typelevel interrupts (a single `Interrupt` enum type, with one variant per interrupt).
const IRQ: super::Interrupt;
/// Enable the interrupt.
#[inline]
unsafe fn enable() {
Self::IRQ.enable()
}
/// Disable the interrupt.
#[inline]
fn disable() {
Self::IRQ.disable()
}
/// Check if interrupt is enabled.
#[inline]
fn is_enabled() -> bool {
Self::IRQ.is_enabled()
}
/// Check if interrupt is pending.
#[inline]
fn is_pending() -> bool {
Self::IRQ.is_pending()
}
/// Set interrupt pending.
#[inline]
fn pend() {
Self::IRQ.pend()
}
/// Unset interrupt pending.
#[inline]
fn unpend() {
Self::IRQ.unpend()
}
/// Get the priority of the interrupt.
#[inline]
fn get_priority() -> crate::interrupt::Priority {
Self::IRQ.get_priority()
}
/// Set the interrupt priority.
#[inline]
fn set_priority(prio: crate::interrupt::Priority) {
Self::IRQ.set_priority(prio)
}
}
$(
#[allow(non_camel_case_types)]
#[doc=stringify!($irqs)]
#[doc=" typelevel interrupt."]
pub enum $irqs {}
impl sealed::Interrupt for $irqs{}
impl Interrupt for $irqs {
const IRQ: super::Interrupt = super::Interrupt::$irqs;
}
)*
/// Interrupt handler trait.
///
/// Drivers that need to handle interrupts implement this trait.
/// The user must ensure `on_interrupt()` is called every time the interrupt fires.
/// Drivers must use use [`Binding`] to assert at compile time that the user has done so.
pub trait Handler<I: Interrupt> {
/// Interrupt handler function.
///
/// Must be called every time the `I` interrupt fires, synchronously from
/// the interrupt handler context.
///
/// # Safety
///
/// This function must ONLY be called from the interrupt handler for `I`.
unsafe fn on_interrupt();
}
/// Compile-time assertion that an interrupt has been bound to a handler.
///
/// For the vast majority of cases, you should use the `bind_interrupts!`
/// macro instead of writing `unsafe impl`s of this trait.
///
/// # Safety
///
/// By implementing this trait, you are asserting that you have arranged for `H::on_interrupt()`
/// to be called every time the `I` interrupt fires.
///
/// This allows drivers to check bindings at compile-time.
pub unsafe trait Binding<I: Interrupt, H: Handler<I>> {}
}
}
};
}
/// Represents an interrupt type that can be configured by embassy to handle
/// interrupts.
pub unsafe trait Interrupt {
/// Return the NVIC interrupt number for this interrupt.
fn number() -> u16;
pub unsafe trait InterruptExt: InterruptNumber + Copy {
/// Enable the interrupt.
#[inline]
unsafe fn enable() {
unsafe fn enable(self) {
compiler_fence(Ordering::SeqCst);
NVIC::unmask(NrWrap(Self::number()))
NVIC::unmask(self)
}
/// Disable the interrupt.
#[inline]
fn disable() {
NVIC::mask(NrWrap(Self::number()));
fn disable(self) {
NVIC::mask(self);
compiler_fence(Ordering::SeqCst);
}
/// Check if interrupt is being handled.
#[inline]
#[cfg(not(armv6m))]
fn is_active() -> bool {
NVIC::is_active(NrWrap(Self::number()))
fn is_active(self) -> bool {
NVIC::is_active(self)
}
/// Check if interrupt is enabled.
#[inline]
fn is_enabled() -> bool {
NVIC::is_enabled(NrWrap(Self::number()))
fn is_enabled(self) -> bool {
NVIC::is_enabled(self)
}
/// Check if interrupt is pending.
#[inline]
fn is_pending() -> bool {
NVIC::is_pending(NrWrap(Self::number()))
fn is_pending(self) -> bool {
NVIC::is_pending(self)
}
/// Set interrupt pending.
#[inline]
fn pend() {
NVIC::pend(NrWrap(Self::number()))
fn pend(self) {
NVIC::pend(self)
}
/// Unset interrupt pending.
#[inline]
fn unpend() {
NVIC::unpend(NrWrap(Self::number()))
fn unpend(self) {
NVIC::unpend(self)
}
/// Get the priority of the interrupt.
#[inline]
fn get_priority() -> Priority {
Priority::from(NVIC::get_priority(NrWrap(Self::number())))
fn get_priority(self) -> Priority {
Priority::from(NVIC::get_priority(self))
}
/// Set the interrupt priority.
#[inline]
fn set_priority(prio: Priority) {
fn set_priority(self, prio: Priority) {
critical_section::with(|_| unsafe {
let mut nvic: cortex_m::peripheral::NVIC = mem::transmute(());
nvic.set_priority(NrWrap(Self::number()), prio.into())
nvic.set_priority(self, prio.into())
})
}
}
unsafe impl<T: InterruptNumber + Copy> InterruptExt for T {}
impl From<u8> for Priority {
fn from(priority: u8) -> Self {
unsafe { mem::transmute(priority & PRIO_MASK) }

12
embassy-lora/src/iv.rs
View File

@ -1,7 +1,7 @@
#[cfg(feature = "stm32wl")]
use embassy_stm32::interrupt;
#[cfg(feature = "stm32wl")]
use embassy_stm32::interrupt::*;
use embassy_stm32::interrupt::InterruptExt;
#[cfg(feature = "stm32wl")]
use embassy_stm32::pac;
#[cfg(feature = "stm32wl")]
@ -20,9 +20,9 @@ use lora_phy::mod_traits::InterfaceVariant;
pub struct InterruptHandler {}
#[cfg(feature = "stm32wl")]
impl interrupt::Handler<interrupt::SUBGHZ_RADIO> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::SUBGHZ_RADIO> for InterruptHandler {
unsafe fn on_interrupt() {
interrupt::SUBGHZ_RADIO::disable();
interrupt::SUBGHZ_RADIO.disable();
IRQ_SIGNAL.signal(());
}
}
@ -45,11 +45,11 @@ where
{
/// Create an InterfaceVariant instance for an stm32wl/sx1262 combination
pub fn new(
_irq: impl interrupt::Binding<interrupt::SUBGHZ_RADIO, InterruptHandler>,
_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::SUBGHZ_RADIO, InterruptHandler>,
rf_switch_rx: Option<CTRL>,
rf_switch_tx: Option<CTRL>,
) -> Result<Self, RadioError> {
interrupt::SUBGHZ_RADIO::disable();
interrupt::SUBGHZ_RADIO.disable();
Ok(Self {
board_type: BoardType::Stm32wlSx1262, // updated when associated with a specific LoRa board
rf_switch_rx,
@ -95,7 +95,7 @@ where
}
async fn await_irq(&mut self) -> Result<(), RadioError> {
unsafe { interrupt::SUBGHZ_RADIO::enable() };
unsafe { interrupt::SUBGHZ_RADIO.enable() };
IRQ_SIGNAL.wait().await;
Ok(())
}

13
embassy-macros/src/lib.rs
View File

@ -156,16 +156,3 @@ pub fn main_wasm(args: TokenStream, item: TokenStream) -> TokenStream {
let f = syn::parse_macro_input!(item as syn::ItemFn);
main::run(args, f, main::wasm()).unwrap_or_else(|x| x).into()
}
#[proc_macro_attribute]
pub fn cortex_m_interrupt(args: TokenStream, item: TokenStream) -> TokenStream {
let args = syn::parse_macro_input!(args as syn::AttributeArgs);
let f = syn::parse_macro_input!(item as syn::ItemFn);
cortex_m_interrupt::run(args, f).unwrap_or_else(|x| x).into()
}
#[proc_macro]
pub fn cortex_m_interrupt_declare(item: TokenStream) -> TokenStream {
let name = syn::parse_macro_input!(item as syn::Ident);
cortex_m_interrupt_declare::run(name).unwrap_or_else(|x| x).into()
}

66
embassy-macros/src/macros/cortex_m_interrupt.rs
View File

@ -1,66 +0,0 @@
use std::iter;
use darling::FromMeta;
use proc_macro2::TokenStream;
use quote::quote;
use syn::{ReturnType, Type, Visibility};
use crate::util::ctxt::Ctxt;
#[derive(Debug, FromMeta)]
struct Args {}
pub fn run(args: syn::AttributeArgs, mut f: syn::ItemFn) -> Result<TokenStream, TokenStream> {
let _args = Args::from_list(&args).map_err(|e| e.write_errors())?;
let ident = f.sig.ident.clone();
let ident_s = ident.to_string();
// XXX should we blacklist other attributes?
let valid_signature = f.sig.constness.is_none()
&& f.vis == Visibility::Inherited
&& f.sig.abi.is_none()
&& f.sig.inputs.is_empty()
&& f.sig.generics.params.is_empty()
&& f.sig.generics.where_clause.is_none()
&& f.sig.variadic.is_none()
&& match f.sig.output {
ReturnType::Default => true,
ReturnType::Type(_, ref ty) => match **ty {
Type::Tuple(ref tuple) => tuple.elems.is_empty(),
Type::Never(..) => true,
_ => false,
},
};
let ctxt = Ctxt::new();
if !valid_signature {
ctxt.error_spanned_by(
&f.sig,
"`#[interrupt]` handlers must have signature `[unsafe] fn() [-> !]`",
);
}
ctxt.check()?;
f.block.stmts = iter::once(
syn::parse2(quote! {{
// Check that this interrupt actually exists
let __irq_exists_check: interrupt::#ident;
}})
.unwrap(),
)
.chain(f.block.stmts)
.collect();
let result = quote!(
#[doc(hidden)]
#[export_name = #ident_s]
#[allow(non_snake_case)]
#f
);
Ok(result)
}

21
embassy-macros/src/macros/cortex_m_interrupt_declare.rs
View File

@ -1,21 +0,0 @@
use proc_macro2::TokenStream;
use quote::{format_ident, quote};
pub fn run(name: syn::Ident) -> Result<TokenStream, TokenStream> {
let name = format_ident!("{}", name);
let doc = format!("{} interrupt.", name);
let result = quote! {
#[doc = #doc]
#[allow(non_camel_case_types)]
pub enum #name{}
unsafe impl ::embassy_cortex_m::interrupt::Interrupt for #name {
fn number() -> u16 {
use cortex_m::interrupt::InterruptNumber;
let irq = InterruptEnum::#name;
irq.number() as u16
}
}
};
Ok(result)
}

2
embassy-macros/src/macros/mod.rs
View File

@ -1,4 +1,2 @@
pub mod cortex_m_interrupt;
pub mod cortex_m_interrupt_declare;
pub mod main;
pub mod task;

11
embassy-nrf/src/buffered_uarte.rs
View File

@ -15,7 +15,6 @@ use core::slice;
use core::sync::atomic::{compiler_fence, AtomicU8, AtomicUsize, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::atomic_ring_buffer::RingBuffer;
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -24,13 +23,13 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
use crate::gpio::sealed::Pin;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self};
use crate::interrupt::typelevel::Interrupt;
use crate::ppi::{
self, AnyConfigurableChannel, AnyGroup, Channel, ConfigurableChannel, Event, Group, Ppi, PpiGroup, Task,
};
use crate::timer::{Instance as TimerInstance, Timer};
use crate::uarte::{apply_workaround_for_enable_anomaly, Config, Instance as UarteInstance};
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
mod sealed {
use super::*;
@ -77,7 +76,7 @@ pub struct InterruptHandler<U: UarteInstance> {
_phantom: PhantomData<U>,
}
impl<U: UarteInstance> interrupt::Handler<U::Interrupt> for InterruptHandler<U> {
impl<U: UarteInstance> interrupt::typelevel::Handler<U::Interrupt> for InterruptHandler<U> {
unsafe fn on_interrupt() {
//trace!("irq: start");
let r = U::regs();
@ -202,7 +201,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
ppi_group: impl Peripheral<P = impl Group> + 'd,
_irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -237,7 +236,7 @@ impl<'d, U: UarteInstance, T: TimerInstance> BufferedUarte<'d, U, T> {
ppi_ch1: impl Peripheral<P = impl ConfigurableChannel> + 'd,
ppi_ch2: impl Peripheral<P = impl ConfigurableChannel> + 'd,
ppi_group: impl Peripheral<P = impl Group> + 'd,
_irq: impl interrupt::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
_irq: impl interrupt::typelevel::Binding<U::Interrupt, InterruptHandler<U>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
cts: impl Peripheral<P = impl GpioPin> + 'd,

56
embassy-nrf/src/chips/nrf52805.rs
View File

@ -208,33 +208,29 @@ impl_ppi_channel!(PPI_CH31, 31 => static);
impl_saadc_input!(P0_04, ANALOG_INPUT2);
impl_saadc_input!(P0_05, ANALOG_INPUT3);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0,
SPIM0_SPIS0_SPI0,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
SWI0_EGU0,
SWI1_EGU1,
SWI2,
SWI3,
SWI4,
SWI5,
);

62
embassy-nrf/src/chips/nrf52810.rs
View File

@ -234,36 +234,32 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0);
declare!(SPIM0_SPIS0_SPI0);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0,
SPIM0_SPIS0_SPI0,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2,
SWI3,
SWI4,
SWI5,
PWM0,
PDM,
);

62
embassy-nrf/src/chips/nrf52811.rs
View File

@ -236,36 +236,32 @@ impl_saadc_input!(P0_29, ANALOG_INPUT5);
impl_saadc_input!(P0_30, ANALOG_INPUT6);
impl_saadc_input!(P0_31, ANALOG_INPUT7);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0);
declare!(SPIM1_SPIS1_SPI1);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2);
declare!(SWI3);
declare!(SWI4);
declare!(SWI5);
declare!(PWM0);
declare!(PDM);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
TWIM0_TWIS0_TWI0_SPIM0_SPIS0_SPI0,
SPIM1_SPIS1_SPI1,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2,
SWI3,
SWI4,
SWI5,
PWM0,
PDM,
);

60
embassy-nrf/src/chips/nrf52820.rs
View File

@ -224,35 +224,31 @@ impl_ppi_channel!(PPI_CH29, 29 => static);
impl_ppi_channel!(PPI_CH30, 30 => static);
impl_ppi_channel!(PPI_CH31, 31 => static);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(GPIOTE);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(USBD);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
GPIOTE,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
TIMER3,
USBD,
);

82
embassy-nrf/src/chips/nrf52832.rs
View File

@ -263,46 +263,42 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(FPU);
declare!(I2S);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
NFCT,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
TIMER3,
TIMER4,
PWM0,
PDM,
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
RTC2,
FPU,
I2S,
);

90
embassy-nrf/src/chips/nrf52833.rs
View File

@ -306,50 +306,46 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(PWM3);
declare!(SPIM3);
declare!(I2S);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
NFCT,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
TIMER3,
TIMER4,
PWM0,
PDM,
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
RTC2,
FPU,
USBD,
UARTE1,
PWM3,
SPIM3,
I2S,
);

94
embassy-nrf/src/chips/nrf52840.rs
View File

@ -311,52 +311,48 @@ impl_saadc_input!(P0_31, ANALOG_INPUT7);
impl_i2s!(I2S, I2S, I2S);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(POWER_CLOCK);
declare!(RADIO);
declare!(UARTE0_UART0);
declare!(SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0);
declare!(SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1);
declare!(NFCT);
declare!(GPIOTE);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(TEMP);
declare!(RNG);
declare!(ECB);
declare!(CCM_AAR);
declare!(WDT);
declare!(RTC1);
declare!(QDEC);
declare!(COMP_LPCOMP);
declare!(SWI0_EGU0);
declare!(SWI1_EGU1);
declare!(SWI2_EGU2);
declare!(SWI3_EGU3);
declare!(SWI4_EGU4);
declare!(SWI5_EGU5);
declare!(TIMER3);
declare!(TIMER4);
declare!(PWM0);
declare!(PDM);
declare!(MWU);
declare!(PWM1);
declare!(PWM2);
declare!(SPIM2_SPIS2_SPI2);
declare!(RTC2);
declare!(FPU);
declare!(USBD);
declare!(UARTE1);
declare!(QSPI);
declare!(CRYPTOCELL);
declare!(PWM3);
declare!(SPIM3);
declare!(I2S);
}
embassy_cortex_m::interrupt_mod!(
POWER_CLOCK,
RADIO,
UARTE0_UART0,
SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0,
SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1,
NFCT,
GPIOTE,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
TEMP,
RNG,
ECB,
CCM_AAR,
WDT,
RTC1,
QDEC,
COMP_LPCOMP,
SWI0_EGU0,
SWI1_EGU1,
SWI2_EGU2,
SWI3_EGU3,
SWI4_EGU4,
SWI5_EGU5,
TIMER3,
TIMER4,
PWM0,
PDM,
MWU,
PWM1,
PWM2,
SPIM2_SPIS2_SPI2,
RTC2,
FPU,
USBD,
UARTE1,
QSPI,
CRYPTOCELL,
PWM3,
SPIM3,
I2S,
);

90
embassy-nrf/src/chips/nrf5340_app.rs
View File

@ -504,50 +504,46 @@ impl_saadc_input!(P0_18, ANALOG_INPUT5);
impl_saadc_input!(P0_19, ANALOG_INPUT6);
impl_saadc_input!(P0_20, ANALOG_INPUT7);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(FPU);
declare!(CACHE);
declare!(SPU);
declare!(CLOCK_POWER);
declare!(SERIAL0);
declare!(SERIAL1);
declare!(SPIM4);
declare!(SERIAL2);
declare!(SERIAL3);
declare!(GPIOTE0);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(RTC1);
declare!(WDT0);
declare!(WDT1);
declare!(COMP_LPCOMP);
declare!(EGU0);
declare!(EGU1);
declare!(EGU2);
declare!(EGU3);
declare!(EGU4);
declare!(EGU5);
declare!(PWM0);
declare!(PWM1);
declare!(PWM2);
declare!(PWM3);
declare!(PDM0);
declare!(I2S0);
declare!(IPC);
declare!(QSPI);
declare!(NFCT);
declare!(GPIOTE1);
declare!(QDEC0);
declare!(QDEC1);
declare!(USBD);
declare!(USBREGULATOR);
declare!(KMU);
declare!(CRYPTOCELL);
}
embassy_cortex_m::interrupt_mod!(
FPU,
CACHE,
SPU,
CLOCK_POWER,
SERIAL0,
SERIAL1,
SPIM4,
SERIAL2,
SERIAL3,
GPIOTE0,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
RTC1,
WDT0,
WDT1,
COMP_LPCOMP,
EGU0,
EGU1,
EGU2,
EGU3,
EGU4,
EGU5,
PWM0,
PWM1,
PWM2,
PWM3,
PDM0,
I2S0,
IPC,
QSPI,
NFCT,
GPIOTE1,
QDEC0,
QDEC1,
USBD,
USBREGULATOR,
KMU,
CRYPTOCELL,
);

48
embassy-nrf/src/chips/nrf5340_net.rs
View File

@ -340,29 +340,25 @@ impl_ppi_channel!(PPI_CH29, 29 => configurable);
impl_ppi_channel!(PPI_CH30, 30 => configurable);
impl_ppi_channel!(PPI_CH31, 31 => configurable);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(CLOCK_POWER);
declare!(RADIO);
declare!(RNG);
declare!(GPIOTE);
declare!(WDT);
declare!(TIMER0);
declare!(ECB);
declare!(AAR_CCM);
declare!(TEMP);
declare!(RTC0);
declare!(IPC);
declare!(SERIAL0);
declare!(EGU0);
declare!(RTC1);
declare!(TIMER1);
declare!(TIMER2);
declare!(SWI0);
declare!(SWI1);
declare!(SWI2);
declare!(SWI3);
}
embassy_cortex_m::interrupt_mod!(
CLOCK_POWER,
RADIO,
RNG,
GPIOTE,
WDT,
TIMER0,
ECB,
AAR_CCM,
TEMP,
RTC0,
IPC,
SERIAL0,
EGU0,
RTC1,
TIMER1,
TIMER2,
SWI0,
SWI1,
SWI2,
SWI3,
);

70
embassy-nrf/src/chips/nrf9160.rs
View File

@ -366,40 +366,36 @@ impl_saadc_input!(P0_18, ANALOG_INPUT5);
impl_saadc_input!(P0_19, ANALOG_INPUT6);
impl_saadc_input!(P0_20, ANALOG_INPUT7);
pub mod irqs {
use embassy_cortex_m::interrupt::_export::declare;
use crate::pac::Interrupt as InterruptEnum;
declare!(SPU);
declare!(CLOCK_POWER);
declare!(UARTE0_SPIM0_SPIS0_TWIM0_TWIS0);
declare!(UARTE1_SPIM1_SPIS1_TWIM1_TWIS1);
declare!(UARTE2_SPIM2_SPIS2_TWIM2_TWIS2);
declare!(UARTE3_SPIM3_SPIS3_TWIM3_TWIS3);
declare!(GPIOTE0);
declare!(SAADC);
declare!(TIMER0);
declare!(TIMER1);
declare!(TIMER2);
declare!(RTC0);
declare!(RTC1);
declare!(WDT);
declare!(EGU0);
declare!(EGU1);
declare!(EGU2);
declare!(EGU3);
declare!(EGU4);
declare!(EGU5);
declare!(PWM0);
declare!(PWM1);
declare!(PWM2);
declare!(PDM);
declare!(PWM3);
declare!(I2S);
declare!(IPC);
declare!(FPU);
declare!(GPIOTE1);
declare!(KMU);
declare!(CRYPTOCELL);
}
embassy_cortex_m::interrupt_mod!(
SPU,
CLOCK_POWER,
UARTE0_SPIM0_SPIS0_TWIM0_TWIS0,
UARTE1_SPIM1_SPIS1_TWIM1_TWIS1,
UARTE2_SPIM2_SPIS2_TWIM2_TWIS2,
UARTE3_SPIM3_SPIS3_TWIM3_TWIS3,
GPIOTE0,
SAADC,
TIMER0,
TIMER1,
TIMER2,
RTC0,
RTC1,
WDT,
EGU0,
EGU1,
EGU2,
EGU3,
EGU4,
EGU5,
PWM0,
PWM1,
PWM2,
PDM,
PWM3,
I2S,
IPC,
FPU,
GPIOTE1,
KMU,
CRYPTOCELL,
);

14
embassy-nrf/src/gpiote.rs
View File

@ -9,7 +9,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Flex, Input, Output, Pin as GpioPin};
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::ppi::{Event, Task};
use crate::{interrupt, pac, peripherals};
@ -75,15 +75,15 @@ pub(crate) fn init(irq_prio: crate::interrupt::Priority) {
// Enable interrupts
#[cfg(any(feature = "nrf5340-app-s", feature = "nrf9160-s"))]
type Irq = interrupt::GPIOTE0;
let irq = interrupt::GPIOTE0;
#[cfg(any(feature = "nrf5340-app-ns", feature = "nrf9160-ns"))]
type Irq = interrupt::GPIOTE1;
let irq = interrupt::GPIOTE1;
#[cfg(any(feature = "_nrf52", feature = "nrf5340-net"))]
type Irq = interrupt::GPIOTE;
let irq = interrupt::GPIOTE;
Irq::unpend();
Irq::set_priority(irq_prio);
unsafe { Irq::enable() };
irq.unpend();
irq.set_priority(irq_prio);
unsafe { irq.enable() };
let g = regs();
g.events_port.write(|w| w);

14
embassy-nrf/src/i2s.rs
View File

@ -13,10 +13,10 @@ use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use crate::gpio::{AnyPin, Pin as GpioPin};
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::pac::i2s::RegisterBlock;
use crate::util::{slice_in_ram_or, slice_ptr_parts};
use crate::{Peripheral, EASY_DMA_SIZE};
use crate::{interrupt, Peripheral, EASY_DMA_SIZE};
/// Type alias for `MultiBuffering` with 2 buffers.
pub type DoubleBuffering<S, const NS: usize> = MultiBuffering<S, 2, NS>;
@ -367,7 +367,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let device = Device::<T>::new();
let s = T::state();
@ -408,7 +408,7 @@ impl<'d, T: Instance> I2S<'d, T> {
/// Create a new I2S in master mode
pub fn new_master(
i2s: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
mck: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
lrck: impl Peripheral<P = impl GpioPin> + 'd,
@ -431,7 +431,7 @@ impl<'d, T: Instance> I2S<'d, T> {
/// Create a new I2S in slave mode
pub fn new_slave(
i2s: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
lrck: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -1173,7 +1173,7 @@ pub(crate) mod sealed {
/// I2S peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_i2s {
@ -1188,7 +1188,7 @@ macro_rules! impl_i2s {
}
}
impl crate::i2s::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

29
embassy-nrf/src/lib.rs
View File

@ -93,21 +93,16 @@ pub mod wdt;
#[cfg_attr(feature = "_nrf9160", path = "chips/nrf9160.rs")]
mod chip;
pub mod interrupt {
//! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
pub use crate::chip::interrupt;
pub use crate::chip::irqs::*;
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
$vis struct $name;
@ -116,17 +111,16 @@ pub mod interrupt {
#[no_mangle]
unsafe extern "C" fn $irq() {
$(
<$handler as $crate::interrupt::Handler<$crate::interrupt::$irq>>::on_interrupt();
<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
)*
}
$(
unsafe impl $crate::interrupt::Binding<$crate::interrupt::$irq, $handler> for $name {}
unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
)*
)*
};
}
}
// Reexports
@ -136,7 +130,6 @@ pub use chip::pac;
pub(crate) use chip::pac;
pub use chip::{peripherals, Peripherals, EASY_DMA_SIZE};
pub use embassy_cortex_m::executor;
pub use embassy_cortex_m::interrupt::_export::interrupt;
pub use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
pub mod config {

13
embassy-nrf/src/pdm.rs
View File

@ -6,7 +6,6 @@ use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use futures::future::poll_fn;
@ -14,15 +13,15 @@ use futures::future::poll_fn;
use crate::chip::EASY_DMA_SIZE;
use crate::gpio::sealed::Pin;
use crate::gpio::{AnyPin, Pin as GpioPin};
use crate::interrupt::{self};
use crate::Peripheral;
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
T::regs().intenclr.write(|w| w.end().clear());
T::state().waker.wake();
@ -53,7 +52,7 @@ impl<'d, T: Instance> Pdm<'d, T> {
/// Create PDM driver
pub fn new(
pdm: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
clk: impl Peripheral<P = impl GpioPin> + 'd,
din: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -274,7 +273,7 @@ pub(crate) mod sealed {
/// PDM peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_pdm {
@ -289,7 +288,7 @@ macro_rules! impl_pdm {
}
}
impl crate::pdm::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

7
embassy-nrf/src/pwm.rs
View File

@ -8,10 +8,9 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::Interrupt;
use crate::ppi::{Event, Task};
use crate::util::slice_in_ram_or;
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
/// SimplePwm is the traditional pwm interface you're probably used to, allowing
/// to simply set a duty cycle across up to four channels.
@ -843,7 +842,7 @@ pub(crate) mod sealed {
/// PWM peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_pwm {
@ -854,7 +853,7 @@ macro_rules! impl_pwm {
}
}
impl crate::pwm::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

12
embassy-nrf/src/qdec.rs
View File

@ -10,7 +10,7 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{AnyPin, Pin as GpioPin};
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
/// Quadrature decoder driver.
@ -50,7 +50,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
T::regs().intenclr.write(|w| w.reportrdy().clear());
T::state().waker.wake();
@ -61,7 +61,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
/// Create a new QDEC.
pub fn new(
qdec: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
a: impl Peripheral<P = impl GpioPin> + 'd,
b: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -73,7 +73,7 @@ impl<'d, T: Instance> Qdec<'d, T> {
/// Create a new QDEC, with a pin for LED output.
pub fn new_with_led(
qdec: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
a: impl Peripheral<P = impl GpioPin> + 'd,
b: impl Peripheral<P = impl GpioPin> + 'd,
led: impl Peripheral<P = impl GpioPin> + 'd,
@ -271,7 +271,7 @@ pub(crate) mod sealed {
/// qdec peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_qdec {
@ -286,7 +286,7 @@ macro_rules! impl_qdec {
}
}
impl crate::qdec::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

12
embassy-nrf/src/qspi.rs
View File

@ -12,12 +12,12 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use embedded_storage::nor_flash::{ErrorType, NorFlash, NorFlashError, NorFlashErrorKind, ReadNorFlash};
use crate::gpio::{self, Pin as GpioPin};
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
pub use crate::pac::qspi::ifconfig0::{
ADDRMODE_A as AddressMode, PPSIZE_A as WritePageSize, READOC_A as ReadOpcode, WRITEOC_A as WriteOpcode,
};
pub use crate::pac::qspi::ifconfig1::SPIMODE_A as SpiMode;
use crate::Peripheral;
use crate::{interrupt, Peripheral};
/// Deep power-down config.
pub struct DeepPowerDownConfig {
@ -120,7 +120,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -143,7 +143,7 @@ impl<'d, T: Instance> Qspi<'d, T> {
/// Create a new QSPI driver.
pub fn new(
qspi: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
csn: impl Peripheral<P = impl GpioPin> + 'd,
io0: impl Peripheral<P = impl GpioPin> + 'd,
@ -644,7 +644,7 @@ pub(crate) mod sealed {
/// QSPI peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_qspi {
@ -659,7 +659,7 @@ macro_rules! impl_qspi {
}
}
impl crate::qspi::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

10
embassy-nrf/src/rng.rs
View File

@ -12,7 +12,7 @@ use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
@ -20,7 +20,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let s = T::state();
let r = T::regs();
@ -89,7 +89,7 @@ impl<'d, T: Instance> Rng<'d, T> {
/// The synchronous API is safe.
pub fn new(
rng: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
) -> Self {
into_ref!(rng);
@ -255,7 +255,7 @@ pub(crate) mod sealed {
/// RNG peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_rng {
@ -270,7 +270,7 @@ macro_rules! impl_rng {
}
}
impl crate::rng::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

10
embassy-nrf/src/saadc.rs
View File

@ -6,7 +6,6 @@ use core::future::poll_fn;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -18,6 +17,7 @@ use saadc::oversample::OVERSAMPLE_A;
use saadc::resolution::VAL_A;
use self::sealed::Input as _;
use crate::interrupt::InterruptExt;
use crate::ppi::{ConfigurableChannel, Event, Ppi, Task};
use crate::timer::{Frequency, Instance as TimerInstance, Timer};
use crate::{interrupt, pac, peripherals, Peripheral};
@ -33,7 +33,7 @@ pub struct InterruptHandler {
_private: (),
}
impl interrupt::Handler<interrupt::SAADC> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::SAADC> for InterruptHandler {
unsafe fn on_interrupt() {
let r = unsafe { &*SAADC::ptr() };
@ -144,7 +144,7 @@ impl<'d, const N: usize> Saadc<'d, N> {
/// Create a new SAADC driver.
pub fn new(
saadc: impl Peripheral<P = peripherals::SAADC> + 'd,
_irq: impl interrupt::Binding<interrupt::SAADC, InterruptHandler> + 'd,
_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::SAADC, InterruptHandler> + 'd,
config: Config,
channel_configs: [ChannelConfig; N],
) -> Self {
@ -189,8 +189,8 @@ impl<'d, const N: usize> Saadc<'d, N> {
// Disable all events interrupts
r.intenclr.write(|w| unsafe { w.bits(0x003F_FFFF) });
interrupt::SAADC::unpend();
unsafe { interrupt::SAADC::enable() };
interrupt::SAADC.unpend();
unsafe { interrupt::SAADC.enable() };
Self { _p: saadc }
}

16
embassy-nrf/src/spim.rs
View File

@ -15,9 +15,9 @@ pub use pac::spim0::frequency::FREQUENCY_A as Frequency;
use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
/// SPIM error
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -63,7 +63,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -84,7 +84,7 @@ impl<'d, T: Instance> Spim<'d, T> {
/// Create a new SPIM driver.
pub fn new(
spim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd,
@ -103,7 +103,7 @@ impl<'d, T: Instance> Spim<'d, T> {
/// Create a new SPIM driver, capable of TX only (MOSI only).
pub fn new_txonly(
spim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -115,7 +115,7 @@ impl<'d, T: Instance> Spim<'d, T> {
/// Create a new SPIM driver, capable of RX only (MISO only).
pub fn new_rxonly(
spim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -408,7 +408,7 @@ pub(crate) mod sealed {
/// SPIM peripheral instance
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_spim {
@ -423,7 +423,7 @@ macro_rules! impl_spim {
}
}
impl crate::spim::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

16
embassy-nrf/src/spis.rs
View File

@ -13,9 +13,9 @@ pub use embedded_hal_02::spi::{Mode, Phase, Polarity, MODE_0, MODE_1, MODE_2, MO
use crate::chip::FORCE_COPY_BUFFER_SIZE;
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin};
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::util::{slice_in_ram_or, slice_ptr_parts, slice_ptr_parts_mut};
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
/// SPIS error
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -68,7 +68,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -94,7 +94,7 @@ impl<'d, T: Instance> Spis<'d, T> {
/// Create a new SPIS driver.
pub fn new(
spis: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd,
@ -115,7 +115,7 @@ impl<'d, T: Instance> Spis<'d, T> {
/// Create a new SPIS driver, capable of TX only (MISO only).
pub fn new_txonly(
spis: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
miso: impl Peripheral<P = impl GpioPin> + 'd,
@ -128,7 +128,7 @@ impl<'d, T: Instance> Spis<'d, T> {
/// Create a new SPIS driver, capable of RX only (MOSI only).
pub fn new_rxonly(
spis: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
cs: impl Peripheral<P = impl GpioPin> + 'd,
sck: impl Peripheral<P = impl GpioPin> + 'd,
mosi: impl Peripheral<P = impl GpioPin> + 'd,
@ -480,7 +480,7 @@ pub(crate) mod sealed {
/// SPIS peripheral instance
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_spis {
@ -495,7 +495,7 @@ macro_rules! impl_spis {
}
}
impl crate::spis::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

10
embassy-nrf/src/temp.rs
View File

@ -8,7 +8,7 @@ use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use fixed::types::I30F2;
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::peripherals::TEMP;
use crate::{interrupt, pac, Peripheral};
@ -17,7 +17,7 @@ pub struct InterruptHandler {
_private: (),
}
impl interrupt::Handler<interrupt::TEMP> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::TEMP> for InterruptHandler {
unsafe fn on_interrupt() {
let r = unsafe { &*pac::TEMP::PTR };
r.intenclr.write(|w| w.datardy().clear());
@ -36,13 +36,13 @@ impl<'d> Temp<'d> {
/// Create a new temperature sensor driver.
pub fn new(
_peri: impl Peripheral<P = TEMP> + 'd,
_irq: impl interrupt::Binding<interrupt::TEMP, InterruptHandler> + 'd,
_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::TEMP, InterruptHandler> + 'd,
) -> Self {
into_ref!(_peri);
// Enable interrupt that signals temperature values
interrupt::TEMP::unpend();
unsafe { interrupt::TEMP::enable() };
interrupt::TEMP.unpend();
unsafe { interrupt::TEMP.enable() };
Self { _peri }
}

6
embassy-nrf/src/time_driver.rs
View File

@ -7,7 +7,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::CriticalSectionMutex as Mutex;
use embassy_time::driver::{AlarmHandle, Driver};
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::{interrupt, pac};
fn rtc() -> &'static pac::rtc0::RegisterBlock {
@ -142,8 +142,8 @@ impl RtcDriver {
// Wait for clear
while r.counter.read().bits() != 0 {}
interrupt::RTC1::set_priority(irq_prio);
unsafe { interrupt::RTC1::enable() };
interrupt::RTC1.set_priority(irq_prio);
unsafe { interrupt::RTC1.enable() };
}
fn on_interrupt(&self) {

5
embassy-nrf/src/timer.rs
View File

@ -8,7 +8,6 @@
use embassy_hal_common::{into_ref, PeripheralRef};
use crate::interrupt::Interrupt;
use crate::ppi::{Event, Task};
use crate::{pac, Peripheral};
@ -29,7 +28,7 @@ pub(crate) mod sealed {
/// Basic Timer instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: crate::interrupt::typelevel::Interrupt;
}
/// Extended timer instance.
@ -44,7 +43,7 @@ macro_rules! impl_timer {
}
}
impl crate::timer::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
($type:ident, $pac_type:ident, $irq:ident) => {

12
embassy-nrf/src/twim.rs
View File

@ -16,9 +16,9 @@ use embassy_time::{Duration, Instant};
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::Pin as GpioPin;
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::util::{slice_in_ram, slice_in_ram_or};
use crate::{gpio, pac, Peripheral};
use crate::{gpio, interrupt, pac, Peripheral};
/// TWI frequency
#[derive(Clone, Copy)]
@ -98,7 +98,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -123,7 +123,7 @@ impl<'d, T: Instance> Twim<'d, T> {
/// Create a new TWI driver.
pub fn new(
twim: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sda: impl Peripheral<P = impl GpioPin> + 'd,
scl: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -750,7 +750,7 @@ pub(crate) mod sealed {
/// TWIM peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_twim {
@ -765,7 +765,7 @@ macro_rules! impl_twim {
}
}
impl crate::twim::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

12
embassy-nrf/src/twis.rs
View File

@ -15,9 +15,9 @@ use embassy_time::{Duration, Instant};
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::Pin as GpioPin;
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::util::slice_in_ram_or;
use crate::{gpio, pac, Peripheral};
use crate::{gpio, interrupt, pac, Peripheral};
/// TWIS config.
#[non_exhaustive]
@ -114,7 +114,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -143,7 +143,7 @@ impl<'d, T: Instance> Twis<'d, T> {
/// Create a new TWIS driver.
pub fn new(
twis: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
sda: impl Peripheral<P = impl GpioPin> + 'd,
scl: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -778,7 +778,7 @@ pub(crate) mod sealed {
/// TWIS peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_twis {
@ -793,7 +793,7 @@ macro_rules! impl_twis {
}
}
impl crate::twis::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

22
embassy-nrf/src/uarte.rs
View File

@ -27,11 +27,11 @@ pub use pac::uarte0::{baudrate::BAUDRATE_A as Baudrate, config::PARITY_A as Pari
use crate::chip::{EASY_DMA_SIZE, FORCE_COPY_BUFFER_SIZE};
use crate::gpio::sealed::Pin as _;
use crate::gpio::{self, AnyPin, Pin as GpioPin, PselBits};
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::ppi::{AnyConfigurableChannel, ConfigurableChannel, Event, Ppi, Task};
use crate::timer::{Frequency, Instance as TimerInstance, Timer};
use crate::util::slice_in_ram_or;
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
/// UARTE config.
#[derive(Clone)]
@ -68,7 +68,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -108,7 +108,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
/// Create a new UARTE without hardware flow control
pub fn new(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -120,7 +120,7 @@ impl<'d, T: Instance> Uarte<'d, T> {
/// Create a new UARTE with hardware flow control (RTS/CTS)
pub fn new_with_rtscts(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
cts: impl Peripheral<P = impl GpioPin> + 'd,
@ -313,7 +313,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
/// Create a new tx-only UARTE without hardware flow control
pub fn new(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
@ -324,7 +324,7 @@ impl<'d, T: Instance> UarteTx<'d, T> {
/// Create a new tx-only UARTE with hardware flow control (RTS/CTS)
pub fn new_with_rtscts(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
txd: impl Peripheral<P = impl GpioPin> + 'd,
cts: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -509,7 +509,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
/// Create a new rx-only UARTE without hardware flow control
pub fn new(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
) -> Self {
@ -520,7 +520,7 @@ impl<'d, T: Instance> UarteRx<'d, T> {
/// Create a new rx-only UARTE with hardware flow control (RTS/CTS)
pub fn new_with_rtscts(
uarte: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rxd: impl Peripheral<P = impl GpioPin> + 'd,
rts: impl Peripheral<P = impl GpioPin> + 'd,
config: Config,
@ -889,7 +889,7 @@ pub(crate) mod sealed {
/// UARTE peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_uarte {
@ -908,7 +908,7 @@ macro_rules! impl_uarte {
}
}
impl crate::uarte::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

12
embassy-nrf/src/usb/mod.rs
View File

@ -18,9 +18,9 @@ use embassy_usb_driver::{Direction, EndpointAddress, EndpointError, EndpointInfo
use pac::usbd::RegisterBlock;
use self::vbus_detect::VbusDetect;
use crate::interrupt::{self, Interrupt};
use crate::interrupt::typelevel::Interrupt;
use crate::util::slice_in_ram;
use crate::{pac, Peripheral};
use crate::{interrupt, pac, Peripheral};
const NEW_AW: AtomicWaker = AtomicWaker::new();
static BUS_WAKER: AtomicWaker = NEW_AW;
@ -34,7 +34,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let regs = T::regs();
@ -98,7 +98,7 @@ impl<'d, T: Instance, V: VbusDetect> Driver<'d, T, V> {
/// Create a new USB driver.
pub fn new(
usb: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
vbus_detect: V,
) -> Self {
into_ref!(usb);
@ -804,7 +804,7 @@ pub(crate) mod sealed {
/// USB peripheral instance.
pub trait Instance: Peripheral<P = Self> + sealed::Instance + 'static + Send {
/// Interrupt for this peripheral.
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
macro_rules! impl_usb {
@ -815,7 +815,7 @@ macro_rules! impl_usb {
}
}
impl crate::usb::Instance for peripherals::$type {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

12
embassy-nrf/src/usb/vbus_detect.rs
View File

@ -7,8 +7,8 @@ use core::task::Poll;
use embassy_sync::waitqueue::AtomicWaker;
use super::BUS_WAKER;
use crate::interrupt::{self, Interrupt};
use crate::pac;
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, pac};
/// Trait for detecting USB VBUS power.
///
@ -29,9 +29,9 @@ pub trait VbusDetect {
}
#[cfg(not(feature = "_nrf5340"))]
type UsbRegIrq = interrupt::POWER_CLOCK;
type UsbRegIrq = interrupt::typelevel::POWER_CLOCK;
#[cfg(feature = "_nrf5340")]
type UsbRegIrq = interrupt::USBREGULATOR;
type UsbRegIrq = interrupt::typelevel::USBREGULATOR;
#[cfg(not(feature = "_nrf5340"))]
type UsbRegPeri = pac::POWER;
@ -43,7 +43,7 @@ pub struct InterruptHandler {
_private: (),
}
impl interrupt::Handler<UsbRegIrq> for InterruptHandler {
impl interrupt::typelevel::Handler<UsbRegIrq> for InterruptHandler {
unsafe fn on_interrupt() {
let regs = unsafe { &*UsbRegPeri::ptr() };
@ -77,7 +77,7 @@ static POWER_WAKER: AtomicWaker = AtomicWaker::new();
impl HardwareVbusDetect {
/// Create a new `VbusDetectNative`.
pub fn new(_irq: impl interrupt::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self {
pub fn new(_irq: impl interrupt::typelevel::Binding<UsbRegIrq, InterruptHandler> + 'static) -> Self {
let regs = unsafe { &*UsbRegPeri::ptr() };
UsbRegIrq::unpend();

16
embassy-rp/src/adc.rs
View File

@ -3,14 +3,14 @@ use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::{Binding, Interrupt};
use embassy_sync::waitqueue::AtomicWaker;
use embedded_hal_02::adc::{Channel, OneShot};
use crate::gpio::Pin;
use crate::interrupt::{self, ADC_IRQ_FIFO};
use crate::interrupt::typelevel::Binding;
use crate::interrupt::InterruptExt;
use crate::peripherals::ADC;
use crate::{pac, peripherals, Peripheral};
use crate::{interrupt, pac, peripherals, Peripheral};
static WAKER: AtomicWaker = AtomicWaker::new();
#[derive(Debug, Clone, Copy, PartialEq, Eq)]
@ -47,7 +47,7 @@ impl<'d> Adc<'d> {
pub fn new(
_inner: impl Peripheral<P = ADC> + 'd,
_irq: impl Binding<ADC_IRQ_FIFO, InterruptHandler>,
_irq: impl Binding<interrupt::typelevel::ADC_IRQ_FIFO, InterruptHandler>,
_config: Config,
) -> Self {
unsafe {
@ -62,10 +62,8 @@ impl<'d> Adc<'d> {
}
// Setup IRQ
unsafe {
ADC_IRQ_FIFO::unpend();
ADC_IRQ_FIFO::enable();
};
interrupt::ADC_IRQ_FIFO.unpend();
unsafe { interrupt::ADC_IRQ_FIFO.enable() };
Self { phantom: PhantomData }
}
@ -164,7 +162,7 @@ pub struct InterruptHandler {
_empty: (),
}
impl interrupt::Handler<ADC_IRQ_FIFO> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::ADC_IRQ_FIFO> for InterruptHandler {
unsafe fn on_interrupt() {
let r = Adc::regs();
r.inte().write(|w| w.set_fifo(false));

8
embassy-rp/src/dma.rs
View File

@ -4,11 +4,11 @@ use core::pin::Pin;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use pac::dma::vals::DataSize;
use crate::interrupt::InterruptExt;
use crate::pac::dma::vals;
use crate::{interrupt, pac, peripherals};
@ -29,12 +29,12 @@ unsafe fn DMA_IRQ_0() {
}
pub(crate) unsafe fn init() {
interrupt::DMA_IRQ_0::disable();
interrupt::DMA_IRQ_0::set_priority(interrupt::Priority::P3);
interrupt::DMA_IRQ_0.disable();
interrupt::DMA_IRQ_0.set_priority(interrupt::Priority::P3);
pac::DMA.inte0().write(|w| w.set_inte0(0xFFFF));
interrupt::DMA_IRQ_0::enable();
interrupt::DMA_IRQ_0.enable();
}
pub unsafe fn read<'a, C: Channel, W: Word>(

8
embassy-rp/src/gpio.rs
View File

@ -3,10 +3,10 @@ use core::future::Future;
use core::pin::Pin as FuturePin;
use core::task::{Context, Poll};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{impl_peripheral, into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use crate::interrupt::InterruptExt;
use crate::pac::common::{Reg, RW};
use crate::pac::SIO;
use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
@ -137,9 +137,9 @@ pub enum InterruptTrigger {
}
pub(crate) unsafe fn init() {
interrupt::IO_IRQ_BANK0::disable();
interrupt::IO_IRQ_BANK0::set_priority(interrupt::Priority::P3);
interrupt::IO_IRQ_BANK0::enable();
interrupt::IO_IRQ_BANK0.disable();
interrupt::IO_IRQ_BANK0.set_priority(interrupt::Priority::P3);
interrupt::IO_IRQ_BANK0.enable();
}
#[interrupt]

13
embassy-rp/src/i2c.rs
View File

@ -2,14 +2,14 @@ use core::future;
use core::marker::PhantomData;
use core::task::Poll;
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use pac::i2c;
use crate::gpio::sealed::Pin;
use crate::gpio::AnyPin;
use crate::{pac, peripherals, Peripheral};
use crate::interrupt::typelevel::{Binding, Interrupt};
use crate::{interrupt, pac, peripherals, Peripheral};
/// I2C error abort reason
#[derive(Debug)]
@ -312,7 +312,7 @@ pub struct InterruptHandler<T: Instance> {
_uart: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
// Mask interrupts and wake any task waiting for this interrupt
unsafe fn on_interrupt() {
let i2c = T::regs();
@ -760,14 +760,15 @@ fn i2c_reserved_addr(addr: u16) -> bool {
}
mod sealed {
use embassy_cortex_m::interrupt::Interrupt;
use embassy_sync::waitqueue::AtomicWaker;
use crate::interrupt;
pub trait Instance {
const TX_DREQ: u8;
const RX_DREQ: u8;
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
fn regs() -> crate::pac::i2c::I2c;
fn reset() -> crate::pac::resets::regs::Peripherals;
@ -803,7 +804,7 @@ macro_rules! impl_instance {
const TX_DREQ: u8 = $tx_dreq;
const RX_DREQ: u8 = $rx_dreq;
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
#[inline]
fn regs() -> pac::i2c::I2c {

65
embassy-rp/src/interrupt.rs
View File

@ -1,65 +0,0 @@
//! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex};
use embassy_cortex_m::interrupt::_export::declare;
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
use crate::pac::Interrupt as InterruptEnum;
declare!(TIMER_IRQ_0);
declare!(TIMER_IRQ_1);
declare!(TIMER_IRQ_2);
declare!(TIMER_IRQ_3);
declare!(PWM_IRQ_WRAP);
declare!(USBCTRL_IRQ);
declare!(XIP_IRQ);
declare!(PIO0_IRQ_0);
declare!(PIO0_IRQ_1);
declare!(PIO1_IRQ_0);
declare!(PIO1_IRQ_1);
declare!(DMA_IRQ_0);
declare!(DMA_IRQ_1);
declare!(IO_IRQ_BANK0);
declare!(IO_IRQ_QSPI);
declare!(SIO_IRQ_PROC0);
declare!(SIO_IRQ_PROC1);
declare!(CLOCKS_IRQ);
declare!(SPI0_IRQ);
declare!(SPI1_IRQ);
declare!(UART0_IRQ);
declare!(UART1_IRQ);
declare!(ADC_IRQ_FIFO);
declare!(I2C0_IRQ);
declare!(I2C1_IRQ);
declare!(RTC_IRQ);
declare!(SWI_IRQ_0);
declare!(SWI_IRQ_1);
declare!(SWI_IRQ_2);
declare!(SWI_IRQ_3);
declare!(SWI_IRQ_4);
declare!(SWI_IRQ_5);
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
$vis struct $name;
$(
#[allow(non_snake_case)]
#[no_mangle]
unsafe extern "C" fn $irq() {
$(
<$handler as $crate::interrupt::Handler<$crate::interrupt::$irq>>::on_interrupt();
)*
}
$(
unsafe impl $crate::interrupt::Binding<$crate::interrupt::$irq, $handler> for $name {}
)*
)*
};
}

64
embassy-rp/src/lib.rs
View File

@ -16,7 +16,6 @@ pub mod flash;
mod float;
pub mod gpio;
pub mod i2c;
pub mod interrupt;
pub mod multicore;
pub mod pwm;
mod reset;
@ -38,13 +37,74 @@ pub mod relocate;
// Reexports
pub use embassy_cortex_m::executor;
pub use embassy_cortex_m::interrupt::_export::interrupt;
pub use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
#[cfg(feature = "unstable-pac")]
pub use rp_pac as pac;
#[cfg(not(feature = "unstable-pac"))]
pub(crate) use rp_pac as pac;
embassy_cortex_m::interrupt_mod!(
TIMER_IRQ_0,
TIMER_IRQ_1,
TIMER_IRQ_2,
TIMER_IRQ_3,
PWM_IRQ_WRAP,
USBCTRL_IRQ,
XIP_IRQ,
PIO0_IRQ_0,
PIO0_IRQ_1,
PIO1_IRQ_0,
PIO1_IRQ_1,
DMA_IRQ_0,
DMA_IRQ_1,
IO_IRQ_BANK0,
IO_IRQ_QSPI,
SIO_IRQ_PROC0,
SIO_IRQ_PROC1,
CLOCKS_IRQ,
SPI0_IRQ,
SPI1_IRQ,
UART0_IRQ,
UART1_IRQ,
ADC_IRQ_FIFO,
I2C0_IRQ,
I2C1_IRQ,
RTC_IRQ,
SWI_IRQ_0,
SWI_IRQ_1,
SWI_IRQ_2,
SWI_IRQ_3,
SWI_IRQ_4,
SWI_IRQ_5,
);
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
$vis struct $name;
$(
#[allow(non_snake_case)]
#[no_mangle]
unsafe extern "C" fn $irq() {
$(
<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
)*
}
$(
unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
)*
)*
};
}
embassy_hal_common::peripherals! {
PIN_0,
PIN_1,

4
embassy-rp/src/multicore.rs
View File

@ -50,7 +50,7 @@
use core::mem::ManuallyDrop;
use core::sync::atomic::{compiler_fence, AtomicBool, Ordering};
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::peripherals::CORE1;
use crate::{gpio, interrupt, pac};
@ -156,7 +156,7 @@ where
IS_CORE1_INIT.store(true, Ordering::Release);
// Enable fifo interrupt on CORE1 for `pause` functionality.
unsafe { interrupt::SIO_IRQ_PROC1::enable() };
unsafe { interrupt::SIO_IRQ_PROC1.enable() };
entry()
}

14
embassy-rp/src/pio.rs
View File

@ -5,7 +5,6 @@ use core::sync::atomic::{compiler_fence, Ordering};
use core::task::{Context, Poll};
use atomic_polyfill::{AtomicU32, AtomicU8};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
use fixed::types::extra::U8;
@ -17,6 +16,7 @@ use pio::{SideSet, Wrap};
use crate::dma::{Channel, Transfer, Word};
use crate::gpio::sealed::Pin as SealedPin;
use crate::gpio::{self, AnyPin, Drive, Level, Pull, SlewRate};
use crate::interrupt::InterruptExt;
use crate::pac::dma::vals::TreqSel;
use crate::relocate::RelocatedProgram;
use crate::{interrupt, pac, peripherals, pio_instr_util, RegExt};
@ -110,15 +110,15 @@ unsafe fn PIO1_IRQ_0() {
}
pub(crate) unsafe fn init() {
interrupt::PIO0_IRQ_0::disable();
interrupt::PIO0_IRQ_0::set_priority(interrupt::Priority::P3);
interrupt::PIO0_IRQ_0.disable();
interrupt::PIO0_IRQ_0.set_priority(interrupt::Priority::P3);
pac::PIO0.irqs(0).inte().write(|m| m.0 = 0);
interrupt::PIO0_IRQ_0::enable();
interrupt::PIO0_IRQ_0.enable();
interrupt::PIO1_IRQ_0::disable();
interrupt::PIO1_IRQ_0::set_priority(interrupt::Priority::P3);
interrupt::PIO1_IRQ_0.disable();
interrupt::PIO1_IRQ_0.set_priority(interrupt::Priority::P3);
pac::PIO1.irqs(0).inte().write(|m| m.0 = 0);
interrupt::PIO1_IRQ_0::enable();
interrupt::PIO1_IRQ_0.enable();
}
/// Future that waits for TX-FIFO to become writable

10
embassy-rp/src/timer.rs
View File

@ -6,7 +6,7 @@ use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::blocking_mutex::Mutex;
use embassy_time::driver::{AlarmHandle, Driver};
use crate::interrupt::Interrupt;
use crate::interrupt::InterruptExt;
use crate::{interrupt, pac};
struct AlarmState {
@ -145,10 +145,10 @@ pub unsafe fn init() {
w.set_alarm(2, true);
w.set_alarm(3, true);
});
interrupt::TIMER_IRQ_0::enable();
interrupt::TIMER_IRQ_1::enable();
interrupt::TIMER_IRQ_2::enable();
interrupt::TIMER_IRQ_3::enable();
interrupt::TIMER_IRQ_0.enable();
interrupt::TIMER_IRQ_1.enable();
interrupt::TIMER_IRQ_2.enable();
interrupt::TIMER_IRQ_3.enable();
}
#[interrupt]

6
embassy-rp/src/uart/buffered.rs
View File

@ -3,14 +3,14 @@ use core::slice;
use core::task::Poll;
use atomic_polyfill::{AtomicU8, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_hal_common::atomic_ring_buffer::RingBuffer;
use embassy_sync::waitqueue::AtomicWaker;
use embassy_time::{Duration, Timer};
use super::*;
use crate::clocks::clk_peri_freq;
use crate::RegExt;
use crate::interrupt::typelevel::{Binding, Interrupt};
use crate::{interrupt, RegExt};
pub struct State {
tx_waker: AtomicWaker,
@ -485,7 +485,7 @@ pub struct BufferedInterruptHandler<T: Instance> {
_uart: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for BufferedInterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
if r.uartdmacr().read().rxdmae() {

10
embassy-rp/src/uart/mod.rs
View File

@ -3,7 +3,6 @@ use core::marker::PhantomData;
use core::task::Poll;
use atomic_polyfill::{AtomicU16, Ordering};
use embassy_cortex_m::interrupt::{self, Binding, Interrupt};
use embassy_futures::select::{select, Either};
use embassy_hal_common::{into_ref, PeripheralRef};
use embassy_sync::waitqueue::AtomicWaker;
@ -14,8 +13,9 @@ use crate::clocks::clk_peri_freq;
use crate::dma::{AnyChannel, Channel};
use crate::gpio::sealed::Pin;
use crate::gpio::AnyPin;
use crate::interrupt::typelevel::{Binding, Interrupt};
use crate::pac::io::vals::{Inover, Outover};
use crate::{pac, peripherals, Peripheral, RegExt};
use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
#[cfg(feature = "nightly")]
mod buffered;
@ -332,7 +332,7 @@ pub struct InterruptHandler<T: Instance> {
_uart: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let uart = T::regs();
if !uart.uartdmacr().read().rxdmae() {
@ -930,7 +930,7 @@ mod sealed {
const TX_DREQ: u8;
const RX_DREQ: u8;
type Interrupt: crate::interrupt::Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
fn regs() -> pac::uart::Uart;
@ -968,7 +968,7 @@ macro_rules! impl_instance {
const TX_DREQ: u8 = $tx_dreq;
const RX_DREQ: u8 = $rx_dreq;
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
fn regs() -> pac::uart::Uart {
pac::$inst

11
embassy-rp/src/usb.rs
View File

@ -4,15 +4,14 @@ use core::slice;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::{self, Binding};
use embassy_sync::waitqueue::AtomicWaker;
use embassy_usb_driver as driver;
use embassy_usb_driver::{
Direction, EndpointAddress, EndpointAllocError, EndpointError, EndpointInfo, EndpointType, Event, Unsupported,
};
use crate::interrupt::Interrupt;
use crate::{pac, peripherals, Peripheral, RegExt};
use crate::interrupt::typelevel::{Binding, Interrupt};
use crate::{interrupt, pac, peripherals, Peripheral, RegExt};
pub(crate) mod sealed {
pub trait Instance {
@ -22,7 +21,7 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
impl crate::usb::sealed::Instance for peripherals::USB {
@ -35,7 +34,7 @@ impl crate::usb::sealed::Instance for peripherals::USB {
}
impl crate::usb::Instance for peripherals::USB {
type Interrupt = crate::interrupt::USBCTRL_IRQ;
type Interrupt = crate::interrupt::typelevel::USBCTRL_IRQ;
}
const EP_COUNT: usize = 16;
@ -249,7 +248,7 @@ pub struct InterruptHandler<T: Instance> {
_uart: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let regs = T::regs();
//let x = regs.istr().read().0;

8
embassy-stm32/build.rs
View File

@ -160,13 +160,11 @@ fn main() {
}
g.extend(quote! {
pub mod interrupt {
use crate::pac::Interrupt as InterruptEnum;
use embassy_cortex_m::interrupt::_export::declare;
embassy_cortex_m::interrupt_mod!(
#(
declare!(#irqs);
#irqs,
)*
}
);
});
// ========

24
embassy-stm32/src/dcmi.rs
View File

@ -8,7 +8,7 @@ use embassy_sync::waitqueue::AtomicWaker;
use crate::dma::Transfer;
use crate::gpio::sealed::AFType;
use crate::gpio::Speed;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
@ -16,7 +16,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let ris = crate::pac::DCMI.ris().read();
if ris.err_ris() {
@ -119,7 +119,7 @@ where
pub fn new_8bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -143,7 +143,7 @@ where
pub fn new_10bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -169,7 +169,7 @@ where
pub fn new_12bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -197,7 +197,7 @@ where
pub fn new_14bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -227,7 +227,7 @@ where
pub fn new_es_8bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -249,7 +249,7 @@ where
pub fn new_es_10bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -273,7 +273,7 @@ where
pub fn new_es_12bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -299,7 +299,7 @@ where
pub fn new_es_14bit(
peri: impl Peripheral<P = T> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
d1: impl Peripheral<P = impl D1Pin<T>> + 'd,
d2: impl Peripheral<P = impl D2Pin<T>> + 'd,
@ -570,7 +570,7 @@ mod sealed {
}
pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
pin_trait!(D0Pin, Instance);
@ -602,7 +602,7 @@ macro_rules! impl_peripheral {
}
impl Instance for crate::peripherals::$inst {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
}

6
embassy-stm32/src/dma/bdma.rs
View File

@ -14,7 +14,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
use super::word::{Word, WordSize};
use super::Dir;
use crate::_generated::BDMA_CHANNEL_COUNT;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac;
use crate::pac::bdma::{regs, vals};
@ -70,8 +70,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, bdma, $block:ident, $signal_name:ident, $irq:ident) => {
crate::interrupt::$irq::set_priority(irq_priority);
crate::interrupt::$irq::enable();
crate::interrupt::typelevel::$irq::set_priority(irq_priority);
crate::interrupt::typelevel::$irq::enable();
};
}
crate::_generated::init_bdma();

6
embassy-stm32/src/dma/dma.rs
View File

@ -13,7 +13,7 @@ use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
use super::word::{Word, WordSize};
use super::Dir;
use crate::_generated::DMA_CHANNEL_COUNT;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::dma::{regs, vals};
use crate::{interrupt, pac};
@ -149,8 +149,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, dma, $block:ident, $signal_name:ident, $irq:ident) => {
interrupt::$irq::set_priority(irq_priority);
interrupt::$irq::enable();
interrupt::typelevel::$irq::set_priority(irq_priority);
interrupt::typelevel::$irq::enable();
};
}
crate::_generated::init_dma();

4
embassy-stm32/src/dma/gpdma.rs
View File

@ -56,8 +56,8 @@ static STATE: State = State::new();
pub(crate) unsafe fn init(irq_priority: Priority) {
foreach_interrupt! {
($peri:ident, gpdma, $block:ident, $signal_name:ident, $irq:ident) => {
crate::interrupt::$irq::set_priority(irq_priority);
crate::interrupt::$irq::enable();
crate::interrupt::typelevel::$irq::set_priority(irq_priority);
crate::interrupt::typelevel::$irq::enable();
};
}
crate::_generated::init_gpdma();

10
embassy-stm32/src/eth/v1/mod.rs
View File

@ -5,7 +5,6 @@ mod tx_desc;
use core::sync::atomic::{fence, Ordering};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, PeripheralRef};
use stm32_metapac::eth::vals::{Apcs, Cr, Dm, DmaomrSr, Fes, Ftf, Ifg, MbProgress, Mw, Pbl, Rsf, St, Tsf};
@ -14,6 +13,7 @@ pub(crate) use self::tx_desc::{TDes, TDesRing};
use super::*;
use crate::gpio::sealed::{AFType, Pin as __GpioPin};
use crate::gpio::AnyPin;
use crate::interrupt::InterruptExt;
#[cfg(eth_v1a)]
use crate::pac::AFIO;
#[cfg(any(eth_v1b, eth_v1c))]
@ -24,7 +24,7 @@ use crate::{interrupt, Peripheral};
/// Interrupt handler.
pub struct InterruptHandler {}
impl interrupt::Handler<interrupt::ETH> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandler {
unsafe fn on_interrupt() {
WAKER.wake();
@ -100,7 +100,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
pub fn new<const TX: usize, const RX: usize>(
queue: &'d mut PacketQueue<TX, RX>,
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<interrupt::ETH, InterruptHandler> + 'd,
_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
@ -267,8 +267,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
P::phy_reset(&mut this);
P::phy_init(&mut this);
interrupt::ETH::unpend();
interrupt::ETH::enable();
interrupt::ETH.unpend();
interrupt::ETH.enable();
this
}

10
embassy-stm32/src/eth/v2/mod.rs
View File

@ -2,20 +2,20 @@ mod descriptors;
use core::sync::atomic::{fence, Ordering};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, PeripheralRef};
pub(crate) use self::descriptors::{RDes, RDesRing, TDes, TDesRing};
use super::*;
use crate::gpio::sealed::{AFType, Pin as _};
use crate::gpio::{AnyPin, Speed};
use crate::interrupt::InterruptExt;
use crate::pac::ETH;
use crate::{interrupt, Peripheral};
/// Interrupt handler.
pub struct InterruptHandler {}
impl interrupt::Handler<interrupt::ETH> for InterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::ETH> for InterruptHandler {
unsafe fn on_interrupt() {
WAKER.wake();
@ -64,7 +64,7 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
pub fn new<const TX: usize, const RX: usize>(
queue: &'d mut PacketQueue<TX, RX>,
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<interrupt::ETH, InterruptHandler> + 'd,
_irq: impl interrupt::typelevel::Binding<interrupt::typelevel::ETH, InterruptHandler> + 'd,
ref_clk: impl Peripheral<P = impl RefClkPin<T>> + 'd,
mdio: impl Peripheral<P = impl MDIOPin<T>> + 'd,
mdc: impl Peripheral<P = impl MDCPin<T>> + 'd,
@ -238,8 +238,8 @@ impl<'d, T: Instance, P: PHY> Ethernet<'d, T, P> {
P::phy_reset(&mut this);
P::phy_init(&mut this);
interrupt::ETH::unpend();
interrupt::ETH::enable();
interrupt::ETH.unpend();
interrupt::ETH.enable();
this
}

4
embassy-stm32/src/exti.rs
View File

@ -354,13 +354,13 @@ impl_exti!(EXTI15, 15);
macro_rules! enable_irq {
($e:ident) => {
crate::interrupt::$e::enable();
crate::interrupt::typelevel::$e::enable();
};
}
/// safety: must be called only once
pub(crate) unsafe fn init() {
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
foreach_exti_irq!(enable_irq);

10
embassy-stm32/src/flash/asynch.rs
View File

@ -1,7 +1,6 @@
use core::marker::PhantomData;
use atomic_polyfill::{fence, Ordering};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::into_ref;
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
@ -11,6 +10,7 @@ use super::{
blocking_read, ensure_sector_aligned, family, get_sector, Async, Error, Flash, FlashLayout, FLASH_BASE, FLASH_SIZE,
WRITE_SIZE,
};
use crate::interrupt::InterruptExt;
use crate::peripherals::FLASH;
use crate::{interrupt, Peripheral};
@ -19,12 +19,12 @@ pub(super) static REGION_ACCESS: Mutex<CriticalSectionRawMutex, ()> = Mutex::new
impl<'d> Flash<'d, Async> {
pub fn new(
p: impl Peripheral<P = FLASH> + 'd,
_irq: impl interrupt::Binding<crate::interrupt::FLASH, InterruptHandler> + 'd,
_irq: impl interrupt::typelevel::Binding<crate::interrupt::typelevel::FLASH, InterruptHandler> + 'd,
) -> Self {
into_ref!(p);
crate::interrupt::FLASH::unpend();
unsafe { crate::interrupt::FLASH::enable() };
crate::interrupt::FLASH.unpend();
unsafe { crate::interrupt::FLASH.enable() };
Self {
inner: p,
@ -49,7 +49,7 @@ impl<'d> Flash<'d, Async> {
/// Interrupt handler
pub struct InterruptHandler;
impl interrupt::Handler<crate::interrupt::FLASH> for InterruptHandler {
impl interrupt::typelevel::Handler<crate::interrupt::typelevel::FLASH> for InterruptHandler {
unsafe fn on_interrupt() {
family::on_interrupt();
}

6
embassy-stm32/src/i2c/mod.rs
View File

@ -1,6 +1,6 @@
#![macro_use]
use crate::interrupt::Interrupt;
use crate::interrupt;
#[cfg_attr(i2c_v1, path = "v1.rs")]
#[cfg_attr(i2c_v2, path = "v2.rs")]
@ -35,7 +35,7 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + 'static {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
pin_trait!(SclPin, Instance);
@ -57,7 +57,7 @@ foreach_interrupt!(
}
impl Instance for peripherals::$inst {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
);

4
embassy-stm32/src/i2c/v1.rs
View File

@ -16,7 +16,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {}
}
@ -57,7 +57,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
_peri: impl Peripheral<P = T> + 'd,
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
tx_dma: impl Peripheral<P = TXDMA> + 'd,
rx_dma: impl Peripheral<P = RXDMA> + 'd,
freq: Hertz,

6
embassy-stm32/src/i2c/v2.rs
View File

@ -3,7 +3,6 @@ use core::future::poll_fn;
use core::marker::PhantomData;
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_embedded_hal::SetConfig;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
@ -13,6 +12,7 @@ use crate::dma::{NoDma, Transfer};
use crate::gpio::sealed::AFType;
use crate::gpio::Pull;
use crate::i2c::{Error, Instance, SclPin, SdaPin};
use crate::interrupt::typelevel::Interrupt;
use crate::pac::i2c;
use crate::time::Hertz;
use crate::{interrupt, Peripheral};
@ -22,7 +22,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let regs = T::regs();
let isr = regs.isr().read();
@ -78,7 +78,7 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
peri: impl Peripheral<P = T> + 'd,
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
tx_dma: impl Peripheral<P = TXDMA> + 'd,
rx_dma: impl Peripheral<P = RXDMA> + 'd,
freq: Hertz,

51
embassy-stm32/src/lib.rs
View File

@ -72,46 +72,39 @@ pub(crate) mod _generated {
include!(concat!(env!("OUT_DIR"), "/_generated.rs"));
}
pub mod interrupt {
//! Interrupt definitions and macros to bind them.
pub use cortex_m::interrupt::{CriticalSection, Mutex};
pub use embassy_cortex_m::interrupt::{Binding, Handler, Interrupt, Priority};
pub use crate::_generated::interrupt;
pub use crate::_generated::interrupt::*;
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
$vis struct $name;
/// Macro to bind interrupts to handlers.
///
/// This defines the right interrupt handlers, and creates a unit struct (like `struct Irqs;`)
/// and implements the right [`Binding`]s for it. You can pass this struct to drivers to
/// prove at compile-time that the right interrupts have been bound.
// developer note: this macro can't be in `embassy-cortex-m` due to the use of `$crate`.
#[macro_export]
macro_rules! bind_interrupts {
($vis:vis struct $name:ident { $($irq:ident => $($handler:ty),*;)* }) => {
$vis struct $name;
$(
#[allow(non_snake_case)]
#[no_mangle]
unsafe extern "C" fn $irq() {
$(
<$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt();
)*
}
$(
#[allow(non_snake_case)]
#[no_mangle]
unsafe extern "C" fn $irq() {
$(
<$handler as $crate::interrupt::Handler<$crate::interrupt::$irq>>::on_interrupt();
)*
}
$(
unsafe impl $crate::interrupt::Binding<$crate::interrupt::$irq, $handler> for $name {}
)*
unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {}
)*
};
}
)*
};
}
// Reexports
pub use _generated::{peripherals, Peripherals};
pub use embassy_cortex_m::executor;
use embassy_cortex_m::interrupt::Priority;
pub use embassy_cortex_m::interrupt::_export::interrupt;
pub use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
#[cfg(feature = "unstable-pac")]
pub use stm32_metapac as pac;

16
embassy-stm32/src/sdmmc/mod.rs
View File

@ -14,7 +14,7 @@ use sdio_host::{BusWidth, CardCapacity, CardStatus, CurrentState, SDStatus, CID,
use crate::dma::NoDma;
use crate::gpio::sealed::{AFType, Pin};
use crate::gpio::{AnyPin, Pull, Speed};
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::sdmmc::Sdmmc as RegBlock;
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
@ -42,7 +42,7 @@ impl<T: Instance> InterruptHandler<T> {
}
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
Self::data_interrupts(false);
T::state().wake();
@ -276,7 +276,7 @@ pub struct Sdmmc<'d, T: Instance, Dma: SdmmcDma<T> = NoDma> {
impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
pub fn new_1bit(
sdmmc: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
@ -310,7 +310,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
pub fn new_4bit(
sdmmc: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
dma: impl Peripheral<P = Dma> + 'd,
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
@ -356,7 +356,7 @@ impl<'d, T: Instance, Dma: SdmmcDma<T>> Sdmmc<'d, T, Dma> {
impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
pub fn new_1bit(
sdmmc: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
@ -389,7 +389,7 @@ impl<'d, T: Instance> Sdmmc<'d, T, NoDma> {
pub fn new_4bit(
sdmmc: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
clk: impl Peripheral<P = impl CkPin<T>> + 'd,
cmd: impl Peripheral<P = impl CmdPin<T>> + 'd,
d0: impl Peripheral<P = impl D0Pin<T>> + 'd,
@ -1401,7 +1401,7 @@ pub(crate) mod sealed {
use super::*;
pub trait Instance {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
fn regs() -> RegBlock;
fn state() -> &'static AtomicWaker;
@ -1490,7 +1490,7 @@ cfg_if::cfg_if! {
foreach_peripheral!(
(sdmmc, $inst:ident) => {
impl sealed::Instance for peripherals::$inst {
type Interrupt = crate::interrupt::$inst;
type Interrupt = crate::interrupt::typelevel::$inst;
fn regs() -> RegBlock {
crate::pac::$inst

2
embassy-stm32/src/time_driver.rs
View File

@ -11,7 +11,7 @@ use embassy_time::driver::{AlarmHandle, Driver};
use embassy_time::TICK_HZ;
use stm32_metapac::timer::regs;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::timer::vals;
use crate::rcc::sealed::RccPeripheral;
use crate::timer::sealed::{Basic16bitInstance as BasicInstance, GeneralPurpose16bitInstance as Instance};

6
embassy-stm32/src/timer/mod.rs
View File

@ -1,6 +1,6 @@
use stm32_metapac::timer::vals;
use crate::interrupt::Interrupt;
use crate::interrupt;
use crate::rcc::sealed::RccPeripheral as __RccPeri;
use crate::rcc::RccPeripheral;
use crate::time::Hertz;
@ -13,7 +13,7 @@ pub mod low_level {
pub(crate) mod sealed {
use super::*;
pub trait Basic16bitInstance: RccPeripheral {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
fn regs() -> crate::pac::timer::TimBasic;
@ -57,7 +57,7 @@ pub trait Basic16bitInstance: sealed::Basic16bitInstance + 'static {}
macro_rules! impl_basic_16bit_timer {
($inst:ident, $irq:ident) => {
impl sealed::Basic16bitInstance for crate::peripherals::$inst {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
fn regs() -> crate::pac::timer::TimBasic {
crate::pac::timer::TimBasic(crate::pac::$inst.0)

18
embassy-stm32/src/tl_mbox/mod.rs
View File

@ -2,7 +2,6 @@ use core::mem::MaybeUninit;
use atomic_polyfill::{compiler_fence, Ordering};
use bit_field::BitField;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral, PeripheralRef};
use embassy_sync::blocking_mutex::raw::CriticalSectionRawMutex;
use embassy_sync::channel::Channel;
@ -15,6 +14,7 @@ use self::shci::{shci_ble_init, ShciBleInitCmdParam};
use self::sys::Sys;
use self::unsafe_linked_list::LinkedListNode;
use crate::interrupt;
use crate::interrupt::InterruptExt;
use crate::peripherals::IPCC;
pub use crate::tl_mbox::ipcc::Config;
use crate::tl_mbox::ipcc::Ipcc;
@ -63,7 +63,7 @@ pub struct FusInfoTable {
/// Interrupt handler.
pub struct ReceiveInterruptHandler {}
impl interrupt::Handler<interrupt::IPCC_C1_RX> for ReceiveInterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_RX> for ReceiveInterruptHandler {
unsafe fn on_interrupt() {
// info!("ipcc rx interrupt");
@ -79,7 +79,7 @@ impl interrupt::Handler<interrupt::IPCC_C1_RX> for ReceiveInterruptHandler {
pub struct TransmitInterruptHandler {}
impl interrupt::Handler<interrupt::IPCC_C1_TX> for TransmitInterruptHandler {
impl interrupt::typelevel::Handler<interrupt::typelevel::IPCC_C1_TX> for TransmitInterruptHandler {
unsafe fn on_interrupt() {
// info!("ipcc tx interrupt");
@ -324,8 +324,8 @@ impl<'d> TlMbox<'d> {
/// initializes low-level transport between CPU1 and BLE stack on CPU2
pub fn new(
ipcc: impl Peripheral<P = IPCC> + 'd,
_irqs: impl interrupt::Binding<interrupt::IPCC_C1_RX, ReceiveInterruptHandler>
+ interrupt::Binding<interrupt::IPCC_C1_TX, TransmitInterruptHandler>,
_irqs: impl interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_RX, ReceiveInterruptHandler>
+ interrupt::typelevel::Binding<interrupt::typelevel::IPCC_C1_TX, TransmitInterruptHandler>,
config: Config,
) -> Self {
into_ref!(ipcc);
@ -379,11 +379,11 @@ impl<'d> TlMbox<'d> {
MemoryManager::enable();
// enable interrupts
crate::interrupt::IPCC_C1_RX::unpend();
crate::interrupt::IPCC_C1_TX::unpend();
crate::interrupt::IPCC_C1_RX.unpend();
crate::interrupt::IPCC_C1_TX.unpend();
unsafe { crate::interrupt::IPCC_C1_RX::enable() };
unsafe { crate::interrupt::IPCC_C1_TX::enable() };
unsafe { crate::interrupt::IPCC_C1_RX.enable() };
unsafe { crate::interrupt::IPCC_C1_TX.enable() };
Self { _ipcc: ipcc }
}

10
embassy-stm32/src/usart/buffered.rs
View File

@ -2,18 +2,18 @@ use core::future::poll_fn;
use core::slice;
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::atomic_ring_buffer::RingBuffer;
use embassy_sync::waitqueue::AtomicWaker;
use super::*;
use crate::interrupt::typelevel::Interrupt;
/// Interrupt handler.
pub struct InterruptHandler<T: BasicInstance> {
_phantom: PhantomData<T>,
}
impl<T: BasicInstance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let state = T::buffered_state();
@ -115,7 +115,7 @@ pub struct BufferedUartRx<'d, T: BasicInstance> {
impl<'d, T: BasicInstance> BufferedUart<'d, T> {
pub fn new(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
tx_buffer: &'d mut [u8],
@ -130,7 +130,7 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
pub fn new_with_rtscts(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
@ -159,7 +159,7 @@ impl<'d, T: BasicInstance> BufferedUart<'d, T> {
#[cfg(not(any(usart_v1, usart_v2)))]
pub fn new_with_de(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
de: impl Peripheral<P = impl DePin<T>> + 'd,

18
embassy-stm32/src/usart/mod.rs
View File

@ -5,13 +5,13 @@ use core::marker::PhantomData;
use core::sync::atomic::{compiler_fence, Ordering};
use core::task::Poll;
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::drop::OnDrop;
use embassy_hal_common::{into_ref, PeripheralRef};
use futures::future::{select, Either};
use crate::dma::{NoDma, Transfer};
use crate::gpio::sealed::AFType;
use crate::interrupt::typelevel::Interrupt;
#[cfg(not(any(usart_v1, usart_v2)))]
#[allow(unused_imports)]
use crate::pac::usart::regs::Isr as Sr;
@ -31,7 +31,7 @@ pub struct InterruptHandler<T: BasicInstance> {
_phantom: PhantomData<T>,
}
impl<T: BasicInstance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
let r = T::regs();
let s = T::state();
@ -281,7 +281,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
/// Useful if you only want Uart Rx. It saves 1 pin and consumes a little less power.
pub fn new(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
rx_dma: impl Peripheral<P = RxDma> + 'd,
config: Config,
@ -294,7 +294,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
pub fn new_with_rts(
peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
rx_dma: impl Peripheral<P = RxDma> + 'd,
@ -650,7 +650,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
peri: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
tx_dma: impl Peripheral<P = TxDma> + 'd,
rx_dma: impl Peripheral<P = RxDma> + 'd,
config: Config,
@ -665,7 +665,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
peri: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
rts: impl Peripheral<P = impl RtsPin<T>> + 'd,
cts: impl Peripheral<P = impl CtsPin<T>> + 'd,
tx_dma: impl Peripheral<P = TxDma> + 'd,
@ -693,7 +693,7 @@ impl<'d, T: BasicInstance, TxDma, RxDma> Uart<'d, T, TxDma, RxDma> {
peri: impl Peripheral<P = T> + 'd,
rx: impl Peripheral<P = impl RxPin<T>> + 'd,
tx: impl Peripheral<P = impl TxPin<T>> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
de: impl Peripheral<P = impl DePin<T>> + 'd,
tx_dma: impl Peripheral<P = TxDma> + 'd,
rx_dma: impl Peripheral<P = RxDma> + 'd,
@ -1179,7 +1179,7 @@ pub(crate) mod sealed {
pub trait BasicInstance: crate::rcc::RccPeripheral {
const KIND: Kind;
type Interrupt: crate::interrupt::Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
fn regs() -> Regs;
fn state() -> &'static State;
@ -1211,7 +1211,7 @@ macro_rules! impl_usart {
($inst:ident, $irq:ident, $kind:expr) => {
impl sealed::BasicInstance for crate::peripherals::$inst {
const KIND: Kind = $kind;
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
fn regs() -> Regs {
Regs(crate::pac::$inst.0)

6
embassy-stm32/src/usb/mod.rs
View File

@ -1,4 +1,4 @@
use crate::interrupt::Interrupt;
use crate::interrupt;
use crate::rcc::RccPeripheral;
#[cfg(feature = "nightly")]
@ -13,7 +13,7 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + RccPeripheral + 'static {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
// Internal PHY pins
@ -29,7 +29,7 @@ foreach_interrupt!(
}
impl Instance for crate::peripherals::$inst {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
);

6
embassy-stm32/src/usb/usb.rs
View File

@ -14,7 +14,7 @@ use embassy_usb_driver::{
use super::{DmPin, DpPin, Instance};
use crate::gpio::sealed::AFType;
use crate::interrupt::Interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::usb::regs;
use crate::pac::usb::vals::{EpType, Stat};
use crate::pac::USBRAM;
@ -26,7 +26,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
unsafe {
let regs = T::regs();
@ -255,7 +255,7 @@ pub struct Driver<'d, T: Instance> {
impl<'d, T: Instance> Driver<'d, T> {
pub fn new(
_usb: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
) -> Self {

10
embassy-stm32/src/usb_otg/mod.rs
View File

@ -1,7 +1,5 @@
use embassy_cortex_m::interrupt::Interrupt;
use crate::peripherals;
use crate::rcc::RccPeripheral;
use crate::{interrupt, peripherals};
#[cfg(feature = "nightly")]
mod usb;
@ -25,7 +23,7 @@ pub(crate) mod sealed {
}
pub trait Instance: sealed::Instance + RccPeripheral {
type Interrupt: Interrupt;
type Interrupt: interrupt::typelevel::Interrupt;
}
// Internal PHY pins
@ -109,7 +107,7 @@ foreach_interrupt!(
}
impl Instance for peripherals::USB_OTG_FS {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
@ -161,7 +159,7 @@ foreach_interrupt!(
}
impl Instance for peripherals::USB_OTG_HS {
type Interrupt = crate::interrupt::$irq;
type Interrupt = crate::interrupt::typelevel::$irq;
}
};
);

8
embassy-stm32/src/usb_otg/usb.rs
View File

@ -3,7 +3,6 @@ use core::marker::PhantomData;
use core::task::Poll;
use atomic_polyfill::{AtomicBool, AtomicU16, Ordering};
use embassy_cortex_m::interrupt::Interrupt;
use embassy_hal_common::{into_ref, Peripheral};
use embassy_sync::waitqueue::AtomicWaker;
use embassy_usb_driver::{
@ -15,6 +14,7 @@ use futures::future::poll_fn;
use super::*;
use crate::gpio::sealed::AFType;
use crate::interrupt;
use crate::interrupt::typelevel::Interrupt;
use crate::pac::otg::{regs, vals};
use crate::rcc::sealed::RccPeripheral;
use crate::time::Hertz;
@ -24,7 +24,7 @@ pub struct InterruptHandler<T: Instance> {
_phantom: PhantomData<T>,
}
impl<T: Instance> interrupt::Handler<T::Interrupt> for InterruptHandler<T> {
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
unsafe fn on_interrupt() {
trace!("irq");
let r = T::regs();
@ -291,7 +291,7 @@ impl<'d, T: Instance> Driver<'d, T> {
/// Endpoint allocation will fail if it is too small.
pub fn new_fs(
_peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
dp: impl Peripheral<P = impl DpPin<T>> + 'd,
dm: impl Peripheral<P = impl DmPin<T>> + 'd,
ep_out_buffer: &'d mut [u8],
@ -322,7 +322,7 @@ impl<'d, T: Instance> Driver<'d, T> {
/// Endpoint allocation will fail if it is too small.
pub fn new_hs_ulpi(
_peri: impl Peripheral<P = T> + 'd,
_irq: impl interrupt::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
ulpi_clk: impl Peripheral<P = impl UlpiClkPin<T>> + 'd,
ulpi_dir: impl Peripheral<P = impl UlpiDirPin<T>> + 'd,
ulpi_nxt: impl Peripheral<P = impl UlpiNxtPin<T>> + 'd,

3
examples/stm32f7/build.rs
View File

@ -1,9 +1,8 @@
//! adapted from https://github.com/stm32-rs/stm32f7xx-hal/blob/master/build.rs
use std::env;
use std::fs::File;
use std::io::prelude::*;
use std::io::{self};
use std::path::PathBuf;
use std::{env, io};
#[derive(Debug)]
enum Error {