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Refactor _from_ram methods to use more readable copy operation

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Til Blechschmidt 2022-03-02 22:48:58 +01:00
parent 3f2d9cfe0a
commit 993428e2d4
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GPG Key ID: 2F4E54D35C8390CB
3 changed files with 18 additions and 23 deletions
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12
embassy-nrf/src/spim.rs
View File

@ -274,9 +274,9 @@ impl<'d, T: Instance> Spim<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying SPIM tx buffer into RAM for DMA"); trace!("Copying SPIM tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
tx_buf[..tx.len()].copy_from_slice(tx); tx_ram_buf.copy_from_slice(tx);
self.blocking_inner_from_ram(rx, &tx_buf[..tx.len()]) self.blocking_inner_from_ram(rx, tx_ram_buf)
} }
Err(error) => Err(error), Err(error) => Err(error),
} }
@ -306,9 +306,9 @@ impl<'d, T: Instance> Spim<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying SPIM tx buffer into RAM for DMA"); trace!("Copying SPIM tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..tx.len()];
tx_buf[..tx.len()].copy_from_slice(tx); tx_ram_buf.copy_from_slice(tx);
self.async_inner_from_ram(rx, &tx_buf[..tx.len()]).await self.async_inner_from_ram(rx, tx_ram_buf).await
} }
Err(error) => Err(error), Err(error) => Err(error),
} }

17
embassy-nrf/src/twim.rs
View File

@ -398,14 +398,9 @@ impl<'d, T: Instance> Twim<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying TWIM tx buffer into RAM for DMA"); trace!("Copying TWIM tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
tx_buf[..wr_buffer.len()].copy_from_slice(wr_buffer); tx_ram_buf.copy_from_slice(wr_buffer);
self.setup_write_read_from_ram( self.setup_write_read_from_ram(address, &tx_ram_buf, rd_buffer, inten)
address,
&tx_buf[..wr_buffer.len()],
rd_buffer,
inten,
)
} }
Err(error) => Err(error), Err(error) => Err(error),
} }
@ -416,9 +411,9 @@ impl<'d, T: Instance> Twim<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying TWIM tx buffer into RAM for DMA"); trace!("Copying TWIM tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let tx_ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..wr_buffer.len()];
tx_buf[..wr_buffer.len()].copy_from_slice(wr_buffer); tx_ram_buf.copy_from_slice(wr_buffer);
self.setup_write_from_ram(address, &tx_buf[..wr_buffer.len()], inten) self.setup_write_from_ram(address, &tx_ram_buf, inten)
} }
Err(error) => Err(error), Err(error) => Err(error),
} }

12
embassy-nrf/src/uarte.rs
View File

@ -247,9 +247,9 @@ impl<'d, T: Instance> UarteTx<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying UARTE tx buffer into RAM for DMA"); trace!("Copying UARTE tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
tx_buf[..buffer.len()].copy_from_slice(buffer); ram_buf.copy_from_slice(buffer);
self.write_from_ram(&tx_buf[..buffer.len()]).await self.write_from_ram(&ram_buf).await
} }
Err(error) => Err(error), Err(error) => Err(error),
} }
@ -314,9 +314,9 @@ impl<'d, T: Instance> UarteTx<'d, T> {
Ok(_) => Ok(()), Ok(_) => Ok(()),
Err(Error::DMABufferNotInDataMemory) => { Err(Error::DMABufferNotInDataMemory) => {
trace!("Copying UARTE tx buffer into RAM for DMA"); trace!("Copying UARTE tx buffer into RAM for DMA");
let mut tx_buf = [0u8; FORCE_COPY_BUFFER_SIZE]; let ram_buf = &mut [0; FORCE_COPY_BUFFER_SIZE][..buffer.len()];
tx_buf[..buffer.len()].copy_from_slice(buffer); ram_buf.copy_from_slice(buffer);
self.blocking_write_from_ram(&tx_buf[..buffer.len()]) self.blocking_write_from_ram(&ram_buf)
} }
Err(error) => Err(error), Err(error) => Err(error),
} }