Merge pull request #1714 from xoviat/dma
stm32/dma: add writable ringbuf
This commit is contained in:
commit
a1fce1b554
@ -9,7 +9,7 @@ use atomic_polyfill::AtomicUsize;
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
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use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
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use super::word::{Word, WordSize};
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use super::Dir;
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use crate::_generated::BDMA_CHANNEL_COUNT;
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@ -395,13 +395,13 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
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}
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}
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pub struct RingBuffer<'a, C: Channel, W: Word> {
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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channel: PeripheralRef<'a, C>,
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ringbuf: DmaRingBuffer<'a, W>,
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ringbuf: ReadableDmaRingBuffer<'a, W>,
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}
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impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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pub unsafe fn new_read(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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@ -442,7 +442,7 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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let mut this = Self {
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channel,
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cr: w,
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ringbuf: DmaRingBuffer::new(buffer),
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ringbuf: ReadableDmaRingBuffer::new(buffer),
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};
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this.clear_irqs();
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@ -513,7 +513,7 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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.await
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}
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/// The capacity of the ringbuffer
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/// The capacity of the ringbuffer.
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pub fn cap(&self) -> usize {
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self.ringbuf.cap()
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}
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@ -550,7 +550,159 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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}
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}
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impl<'a, C: Channel, W: Word> Drop for RingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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}
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pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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channel: PeripheralRef<'a, C>,
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ringbuf: WritableDmaRingBuffer<'a, W>,
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}
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impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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pub unsafe fn new_write(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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peri_addr: *mut W,
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buffer: &'a mut [W],
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_options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let len = buffer.len();
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assert!(len > 0 && len <= 0xFFFF);
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let dir = Dir::MemoryToPeripheral;
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let data_size = W::size();
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let channel_number = channel.num();
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let dma = channel.regs();
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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#[cfg(bdma_v2)]
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critical_section::with(|_| channel.regs().cselr().modify(|w| w.set_cs(channel.num(), _request)));
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let mut w = regs::Cr(0);
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w.set_psize(data_size.into());
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w.set_msize(data_size.into());
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w.set_minc(vals::Inc::ENABLED);
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w.set_dir(dir.into());
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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w.set_circ(vals::Circ::ENABLED);
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w.set_pl(vals::Pl::VERYHIGH);
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w.set_en(true);
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let buffer_ptr = buffer.as_mut_ptr();
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let mut this = Self {
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channel,
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cr: w,
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ringbuf: WritableDmaRingBuffer::new(buffer),
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};
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this.clear_irqs();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, _request);
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let ch = dma.ch(channel_number);
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ch.par().write_value(peri_addr as u32);
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ch.mar().write_value(buffer_ptr as u32);
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ch.ndtr().write(|w| w.set_ndt(len as u16));
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this
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}
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pub fn start(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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ch.cr().write_value(self.cr)
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}
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pub fn clear(&mut self) {
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self.ringbuf.clear(DmaCtrlImpl(self.channel.reborrow()));
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}
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/// Write elements to the ring buffer
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/// Return a tuple of the length written and the length remaining in the buffer
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pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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self.ringbuf.write(DmaCtrlImpl(self.channel.reborrow()), buf)
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}
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/// Write an exact number of elements to the ringbuffer.
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pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
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use core::future::poll_fn;
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use core::sync::atomic::compiler_fence;
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let mut written_data = 0;
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let buffer_len = buffer.len();
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poll_fn(|cx| {
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self.set_waker(cx.waker());
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compiler_fence(Ordering::SeqCst);
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match self.write(&buffer[written_data..buffer_len]) {
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Ok((len, remaining)) => {
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written_data += len;
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if written_data == buffer_len {
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Poll::Ready(Ok(remaining))
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} else {
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Poll::Pending
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}
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}
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Err(e) => Poll::Ready(Err(e)),
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}
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})
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.await
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}
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/// The capacity of the ringbuffer.
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pub fn cap(&self) -> usize {
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self.ringbuf.cap()
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}
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pub fn set_waker(&mut self, waker: &Waker) {
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STATE.ch_wakers[self.channel.index()].register(waker);
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}
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fn clear_irqs(&mut self) {
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let dma = self.channel.regs();
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dma.ifcr().write(|w| {
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w.set_htif(self.channel.num(), true);
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w.set_tcif(self.channel.num(), true);
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w.set_teif(self.channel.num(), true);
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});
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}
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().ch(self.channel.num());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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// If the channel is enabled and transfer is not completed, we need to perform
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// two separate write access to the CR register to disable the channel.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().ch(self.channel.num());
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ch.cr().read().en()
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}
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}
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impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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@ -7,7 +7,7 @@ use core::task::{Context, Poll, Waker};
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use embassy_hal_internal::{into_ref, Peripheral, PeripheralRef};
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use embassy_sync::waitqueue::AtomicWaker;
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use super::ringbuffer::{DmaCtrl, DmaRingBuffer, OverrunError};
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use super::ringbuffer::{DmaCtrl, OverrunError, ReadableDmaRingBuffer, WritableDmaRingBuffer};
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use super::word::{Word, WordSize};
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use super::Dir;
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use crate::_generated::DMA_CHANNEL_COUNT;
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@ -625,13 +625,13 @@ impl<'a, C: Channel> DmaCtrl for DmaCtrlImpl<'a, C> {
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}
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}
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pub struct RingBuffer<'a, C: Channel, W: Word> {
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pub struct ReadableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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channel: PeripheralRef<'a, C>,
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ringbuf: DmaRingBuffer<'a, W>,
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ringbuf: ReadableDmaRingBuffer<'a, W>,
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}
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impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> ReadableRingBuffer<'a, C, W> {
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pub unsafe fn new_read(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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@ -677,7 +677,7 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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let mut this = Self {
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channel,
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cr: w,
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ringbuf: DmaRingBuffer::new(buffer),
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ringbuf: ReadableDmaRingBuffer::new(buffer),
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};
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this.clear_irqs();
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@ -797,7 +797,176 @@ impl<'a, C: Channel, W: Word> RingBuffer<'a, C, W> {
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}
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}
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impl<'a, C: Channel, W: Word> Drop for RingBuffer<'a, C, W> {
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impl<'a, C: Channel, W: Word> Drop for ReadableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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// "Subsequent reads and writes cannot be moved ahead of preceding reads."
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fence(Ordering::SeqCst);
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}
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}
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pub struct WritableRingBuffer<'a, C: Channel, W: Word> {
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cr: regs::Cr,
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channel: PeripheralRef<'a, C>,
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ringbuf: WritableDmaRingBuffer<'a, W>,
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}
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impl<'a, C: Channel, W: Word> WritableRingBuffer<'a, C, W> {
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pub unsafe fn new_write(
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channel: impl Peripheral<P = C> + 'a,
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_request: Request,
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peri_addr: *mut W,
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buffer: &'a mut [W],
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options: TransferOptions,
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) -> Self {
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into_ref!(channel);
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let len = buffer.len();
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assert!(len > 0 && len <= 0xFFFF);
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let dir = Dir::MemoryToPeripheral;
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let data_size = W::size();
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let channel_number = channel.num();
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let dma = channel.regs();
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// "Preceding reads and writes cannot be moved past subsequent writes."
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fence(Ordering::SeqCst);
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let mut w = regs::Cr(0);
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w.set_dir(dir.into());
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w.set_msize(data_size.into());
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w.set_psize(data_size.into());
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w.set_pl(vals::Pl::VERYHIGH);
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w.set_minc(vals::Inc::INCREMENTED);
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w.set_pinc(vals::Inc::FIXED);
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w.set_teie(true);
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w.set_htie(options.half_transfer_ir);
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w.set_tcie(true);
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w.set_circ(vals::Circ::ENABLED);
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#[cfg(dma_v1)]
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w.set_trbuff(true);
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#[cfg(dma_v2)]
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w.set_chsel(_request);
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w.set_pburst(options.pburst.into());
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w.set_mburst(options.mburst.into());
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w.set_pfctrl(options.flow_ctrl.into());
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w.set_en(true);
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let buffer_ptr = buffer.as_mut_ptr();
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let mut this = Self {
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channel,
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cr: w,
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ringbuf: WritableDmaRingBuffer::new(buffer),
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};
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this.clear_irqs();
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#[cfg(dmamux)]
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super::dmamux::configure_dmamux(&mut *this.channel, _request);
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let ch = dma.st(channel_number);
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ch.par().write_value(peri_addr as u32);
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ch.m0ar().write_value(buffer_ptr as u32);
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ch.ndtr().write_value(regs::Ndtr(len as _));
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ch.fcr().write(|w| {
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if let Some(fth) = options.fifo_threshold {
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// FIFO mode
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w.set_dmdis(vals::Dmdis::DISABLED);
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w.set_fth(fth.into());
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} else {
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// Direct mode
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w.set_dmdis(vals::Dmdis::ENABLED);
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}
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});
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this
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}
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pub fn start(&mut self) {
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let ch = self.channel.regs().st(self.channel.num());
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ch.cr().write_value(self.cr);
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}
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pub fn clear(&mut self) {
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self.ringbuf.clear(DmaCtrlImpl(self.channel.reborrow()));
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}
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/// Write elements from the ring buffer
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/// Return a tuple of the length written and the length remaining in the buffer
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pub fn write(&mut self, buf: &[W]) -> Result<(usize, usize), OverrunError> {
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self.ringbuf.write(DmaCtrlImpl(self.channel.reborrow()), buf)
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}
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/// Write an exact number of elements to the ringbuffer.
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pub async fn write_exact(&mut self, buffer: &[W]) -> Result<usize, OverrunError> {
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use core::future::poll_fn;
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use core::sync::atomic::compiler_fence;
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let mut written_data = 0;
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let buffer_len = buffer.len();
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poll_fn(|cx| {
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self.set_waker(cx.waker());
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compiler_fence(Ordering::SeqCst);
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match self.write(&buffer[written_data..buffer_len]) {
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Ok((len, remaining)) => {
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written_data += len;
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if written_data == buffer_len {
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Poll::Ready(Ok(remaining))
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} else {
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Poll::Pending
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}
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}
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Err(e) => Poll::Ready(Err(e)),
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}
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})
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.await
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}
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// The capacity of the ringbuffer
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pub fn cap(&self) -> usize {
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self.ringbuf.cap()
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}
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pub fn set_waker(&mut self, waker: &Waker) {
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STATE.ch_wakers[self.channel.index()].register(waker);
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}
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fn clear_irqs(&mut self) {
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let channel_number = self.channel.num();
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let dma = self.channel.regs();
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let isrn = channel_number / 4;
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let isrbit = channel_number % 4;
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dma.ifcr(isrn).write(|w| {
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w.set_htif(isrbit, true);
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w.set_tcif(isrbit, true);
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w.set_teif(isrbit, true);
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});
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}
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pub fn request_stop(&mut self) {
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let ch = self.channel.regs().st(self.channel.num());
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// Disable the channel. Keep the IEs enabled so the irqs still fire.
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ch.cr().write(|w| {
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w.set_teie(true);
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w.set_htie(true);
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w.set_tcie(true);
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});
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}
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pub fn is_running(&mut self) -> bool {
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let ch = self.channel.regs().st(self.channel.num());
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ch.cr().read().en()
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}
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}
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impl<'a, C: Channel, W: Word> Drop for WritableRingBuffer<'a, C, W> {
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fn drop(&mut self) {
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self.request_stop();
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while self.is_running() {}
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|
@ -29,7 +29,7 @@ use super::word::Word;
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/// | | | |
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/// +- end --------------------+ +- start ----------------+
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/// ```
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pub struct DmaRingBuffer<'a, W: Word> {
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pub struct ReadableDmaRingBuffer<'a, W: Word> {
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pub(crate) dma_buf: &'a mut [W],
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start: usize,
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}
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@ -51,7 +51,7 @@ pub trait DmaCtrl {
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fn reset_complete_count(&mut self) -> usize;
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}
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impl<'a, W: Word> DmaRingBuffer<'a, W> {
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impl<'a, W: Word> ReadableDmaRingBuffer<'a, W> {
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pub fn new(dma_buf: &'a mut [W]) -> Self {
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Self { dma_buf, start: 0 }
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}
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@ -197,6 +197,112 @@ impl<'a, W: Word> DmaRingBuffer<'a, W> {
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length
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}
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}
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pub struct WritableDmaRingBuffer<'a, W: Word> {
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pub(crate) dma_buf: &'a mut [W],
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end: usize,
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}
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impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
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pub fn new(dma_buf: &'a mut [W]) -> Self {
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Self { dma_buf, end: 0 }
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}
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/// Reset the ring buffer to its initial state
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pub fn clear(&mut self, mut dma: impl DmaCtrl) {
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self.end = 0;
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dma.reset_complete_count();
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}
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/// The capacity of the ringbuffer
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pub const fn cap(&self) -> usize {
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self.dma_buf.len()
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}
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/// The current position of the ringbuffer
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fn pos(&self, remaining_transfers: usize) -> usize {
|
||||
self.cap() - remaining_transfers
|
||||
}
|
||||
|
||||
/// Write elements from the ring buffer
|
||||
/// Return a tuple of the length written and the capacity remaining to be written in the buffer
|
||||
pub fn write(&mut self, mut dma: impl DmaCtrl, buf: &[W]) -> Result<(usize, usize), OverrunError> {
|
||||
let start = self.pos(dma.get_remaining_transfers());
|
||||
if start > self.end {
|
||||
// The occupied portion in the ring buffer DOES wrap
|
||||
let len = self.copy_from(buf, self.end..start);
|
||||
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
// Confirm that the DMA is not inside data we could have written
|
||||
let (pos, complete_count) =
|
||||
critical_section::with(|_| (self.pos(dma.get_remaining_transfers()), dma.get_complete_count()));
|
||||
if (pos >= self.end && pos < start) || (complete_count > 0 && pos >= start) || complete_count > 1 {
|
||||
Err(OverrunError)
|
||||
} else {
|
||||
self.end = (self.end + len) % self.cap();
|
||||
|
||||
Ok((len, self.cap() - (start - self.end)))
|
||||
}
|
||||
} else if start == self.end && dma.get_complete_count() == 0 {
|
||||
Ok((0, 0))
|
||||
} else if start <= self.end && self.end + buf.len() < self.cap() {
|
||||
// The occupied portion in the ring buffer DOES NOT wrap
|
||||
// and copying elements into the buffer WILL NOT cause it to
|
||||
|
||||
// Copy into the dma buffer
|
||||
let len = self.copy_from(buf, self.end..self.cap());
|
||||
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
// Confirm that the DMA is not inside data we could have written
|
||||
let pos = self.pos(dma.get_remaining_transfers());
|
||||
if pos > self.end || pos < start || dma.get_complete_count() > 1 {
|
||||
Err(OverrunError)
|
||||
} else {
|
||||
self.end = (self.end + len) % self.cap();
|
||||
|
||||
Ok((len, self.cap() - (self.end - start)))
|
||||
}
|
||||
} else {
|
||||
// The occupied portion in the ring buffer DOES NOT wrap
|
||||
// and copying elements into the buffer WILL cause it to
|
||||
|
||||
let tail = self.copy_from(buf, self.end..self.cap());
|
||||
let head = self.copy_from(&buf[tail..], 0..start);
|
||||
|
||||
compiler_fence(Ordering::SeqCst);
|
||||
|
||||
// Confirm that the DMA is not inside data we could have written
|
||||
let pos = self.pos(dma.get_remaining_transfers());
|
||||
if pos > self.end || pos < start || dma.reset_complete_count() > 1 {
|
||||
Err(OverrunError)
|
||||
} else {
|
||||
self.end = head;
|
||||
|
||||
Ok((tail + head, self.cap() - (start - self.end)))
|
||||
}
|
||||
}
|
||||
}
|
||||
/// Copy into the dma buffer at `data_range` from `buf`
|
||||
fn copy_from(&mut self, buf: &[W], data_range: Range<usize>) -> usize {
|
||||
// Limit the number of elements that can be copied
|
||||
let length = usize::min(data_range.len(), buf.len());
|
||||
|
||||
// Copy into dma buffer from read buffer
|
||||
// We need to do it like this instead of a simple copy_from_slice() because
|
||||
// reading from a part of memory that may be simultaneously written to is unsafe
|
||||
unsafe {
|
||||
let dma_buf = self.dma_buf.as_mut_ptr();
|
||||
|
||||
for i in 0..length {
|
||||
core::ptr::write_volatile(dma_buf.offset((data_range.start + i) as isize), buf[i]);
|
||||
}
|
||||
}
|
||||
|
||||
length
|
||||
}
|
||||
}
|
||||
#[cfg(test)]
|
||||
mod tests {
|
||||
use core::array;
|
||||
@ -263,7 +369,7 @@ mod tests {
|
||||
#[test]
|
||||
fn empty_and_read_not_started() {
|
||||
let mut dma_buf = [0u8; 16];
|
||||
let ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
}
|
||||
@ -273,7 +379,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
@ -314,7 +420,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
@ -349,7 +455,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
@ -384,7 +490,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
@ -420,7 +526,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
@ -454,7 +560,7 @@ mod tests {
|
||||
let mut dma = TestCircularTransfer::new(16);
|
||||
|
||||
let mut dma_buf: [u8; 16] = array::from_fn(|idx| idx as u8); // 0, 1, ..., 15
|
||||
let mut ringbuf = DmaRingBuffer::new(&mut dma_buf);
|
||||
let mut ringbuf = ReadableDmaRingBuffer::new(&mut dma_buf);
|
||||
|
||||
assert_eq!(0, ringbuf.start);
|
||||
assert_eq!(16, ringbuf.cap());
|
||||
|
@ -6,12 +6,12 @@ use embassy_hal_internal::PeripheralRef;
|
||||
use futures::future::{select, Either};
|
||||
|
||||
use super::{clear_interrupt_flags, rdr, sr, BasicInstance, Error, UartRx};
|
||||
use crate::dma::RingBuffer;
|
||||
use crate::dma::ReadableRingBuffer;
|
||||
use crate::usart::{Regs, Sr};
|
||||
|
||||
pub struct RingBufferedUartRx<'d, T: BasicInstance, RxDma: super::RxDma<T>> {
|
||||
_peri: PeripheralRef<'d, T>,
|
||||
ring_buf: RingBuffer<'d, RxDma, u8>,
|
||||
ring_buf: ReadableRingBuffer<'d, RxDma, u8>,
|
||||
}
|
||||
|
||||
impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
|
||||
@ -24,7 +24,7 @@ impl<'d, T: BasicInstance, RxDma: super::RxDma<T>> UartRx<'d, T, RxDma> {
|
||||
let request = self.rx_dma.request();
|
||||
let opts = Default::default();
|
||||
|
||||
let ring_buf = unsafe { RingBuffer::new_read(self.rx_dma, request, rdr(T::regs()), dma_buf, opts) };
|
||||
let ring_buf = unsafe { ReadableRingBuffer::new_read(self.rx_dma, request, rdr(T::regs()), dma_buf, opts) };
|
||||
|
||||
RingBufferedUartRx {
|
||||
_peri: self._peri,
|
||||
|
Loading…
Reference in New Issue
Block a user