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stm32/spi: fix occasional data corruption

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Need to clear the rx fifo before enabling rx dma.
This commit is contained in:
Patrick Oppenlander 2023-03-01 10:10:40 +11:00
parent dda5a4cc9d
commit aabc275186
1 changed files with 4 additions and 2 deletions
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6
embassy-stm32/src/spi/mod.rs
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@ -456,13 +456,14 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| { T::REGS.cr1().modify(|w| {
w.set_spe(false); w.set_spe(false);
}); });
set_rxdmaen(T::REGS, true);
} }
// SPIv3 clears rxfifo on SPE=0 // SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))] #[cfg(not(any(spi_v3, spi_v4)))]
flush_rx_fifo(T::REGS); flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
let clock_byte_count = data.len(); let clock_byte_count = data.len();
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
@ -510,13 +511,14 @@ impl<'d, T: Instance, Tx, Rx> Spi<'d, T, Tx, Rx> {
T::REGS.cr1().modify(|w| { T::REGS.cr1().modify(|w| {
w.set_spe(false); w.set_spe(false);
}); });
set_rxdmaen(T::REGS, true);
} }
// SPIv3 clears rxfifo on SPE=0 // SPIv3 clears rxfifo on SPE=0
#[cfg(not(any(spi_v3, spi_v4)))] #[cfg(not(any(spi_v3, spi_v4)))]
flush_rx_fifo(T::REGS); flush_rx_fifo(T::REGS);
set_rxdmaen(T::REGS, true);
let rx_request = self.rxdma.request(); let rx_request = self.rxdma.request();
let rx_src = T::REGS.rx_ptr(); let rx_src = T::REGS.rx_ptr();
unsafe { self.rxdma.start_read(rx_request, rx_src, read, Default::default()) }; unsafe { self.rxdma.start_read(rx_request, rx_src, read, Default::default()) };