rp: fix async SPI read and write
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336ebe54c0
commit
ab1a6889a6
@ -56,6 +56,25 @@ pub unsafe fn read<'a, C: Channel, W: Word>(
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)
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}
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pub unsafe fn read_repeated<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const W,
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len: usize,
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dreq: u8,
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) -> Transfer<'a, C> {
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let mut dummy: u32 = 0;
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copy_inner(
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ch,
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from as *const u32,
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&mut dummy as *mut u32,
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len,
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W::size(),
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false,
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false,
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dreq,
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)
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}
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pub unsafe fn write<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: *const [W],
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@ -75,6 +94,25 @@ pub unsafe fn write<'a, C: Channel, W: Word>(
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)
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}
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pub unsafe fn write_repeated<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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to: *mut W,
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len: usize,
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dreq: u8,
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) -> Transfer<'a, C> {
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let dummy: u32 = 0;
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copy_inner(
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ch,
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&dummy as *const u32,
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to as *mut u32,
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len,
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W::size(),
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false,
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false,
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dreq,
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)
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}
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pub unsafe fn copy<'a, C: Channel, W: Word>(
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ch: impl Peripheral<P = C> + 'a,
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from: &[W],
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@ -325,30 +325,53 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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}
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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unsafe {
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self.inner.regs().dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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});
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})
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(ch, buffer, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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crate::dma::write(tx_ch, buffer, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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};
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transfer.await;
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read_repeated(
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rx_ch,
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self.inner.regs().dr().ptr() as *const u8,
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buffer.len(),
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T::RX_DREQ,
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)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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}
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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let ch = self.rx_dma.as_mut().unwrap();
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let transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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unsafe {
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self.inner.regs().dmacr().write(|reg| {
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reg.set_rxdmae(true);
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});
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reg.set_txdmae(true);
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})
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(ch, self.inner.regs().dr().ptr() as *const _, buffer, T::RX_DREQ)
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crate::dma::write_repeated(tx_ch, self.inner.regs().dr().ptr() as *mut u8, buffer.len(), T::TX_DREQ)
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};
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transfer.await;
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, buffer, T::RX_DREQ)
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};
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join(tx_transfer, rx_transfer).await;
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Ok(())
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}
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@ -364,20 +387,20 @@ impl<'d, T: Instance> Spi<'d, T, Async> {
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let (_, from_len) = crate::dma::slice_ptr_parts(tx_ptr);
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let (_, to_len) = crate::dma::slice_ptr_parts_mut(rx_ptr);
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assert_eq!(from_len, to_len);
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unsafe {
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self.inner.regs().dmacr().write(|reg| {
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reg.set_rxdmae(true);
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reg.set_txdmae(true);
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})
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};
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let tx_ch = self.tx_dma.as_mut().unwrap();
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let tx_transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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reg.set_txdmae(true);
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::write(tx_ch, tx_ptr, self.inner.regs().dr().ptr() as *mut _, T::TX_DREQ)
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};
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let rx_ch = self.rx_dma.as_mut().unwrap();
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let rx_transfer = unsafe {
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self.inner.regs().dmacr().modify(|reg| {
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reg.set_rxdmae(true);
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});
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// If we don't assign future to a variable, the data register pointer
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// is held across an await and makes the future non-Send.
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crate::dma::read(rx_ch, self.inner.regs().dr().ptr() as *const _, rx_ptr, T::RX_DREQ)
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