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Don't read data register to clear flags on usart v3 ^& v4

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This commit is contained in:
Peter Gibson 2023-06-18 08:45:58 +10:00
parent d236f3dbf9
commit b4f96e192c
1 changed files with 4 additions and 2 deletions
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6
embassy-stm32/src/usart/buffered.rs
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@ -21,8 +21,10 @@ impl<T: BasicInstance> interrupt::typelevel::Handler<T::Interrupt> for Interrupt
// RX // RX
unsafe { unsafe {
let sr = sr(r).read(); let sr = sr(r).read();
// Reading DR clears the rxne, error and idle interrupt flags on v1. // On v1 & v2, reading DR clears the rxne, error and idle interrupt
let dr = if sr.ore() || sr.idle() || sr.rxne() { // flags. Keep this close to the SR read to reduce the chance of a
// flag being set in-between.
let dr = if sr.rxne() || cfg!(any(usart_v1, usart_v2)) && (sr.ore() || sr.idle()) {
Some(rdr(r).read_volatile()) Some(rdr(r).read_volatile())
} else { } else {
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