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Add pwr for L1 and update RCC to new reg block

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Ulf Lilleengen 2021-09-23 14:43:17 +02:00 committed by Ulf Lilleengen
parent d5b21b881e
commit b6fc19182b
4 changed files with 25 additions and 22 deletions
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1
embassy-stm32/src/pwr/l1.rs Normal file
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@ -0,0 +1 @@

1
embassy-stm32/src/pwr/mod.rs
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@ -2,6 +2,7 @@
#[cfg_attr(pwr_f4, path = "f4.rs")] #[cfg_attr(pwr_f4, path = "f4.rs")]
#[cfg_attr(pwr_wl5, path = "wl5.rs")] #[cfg_attr(pwr_wl5, path = "wl5.rs")]
#[cfg_attr(pwr_g0, path = "g0.rs")] #[cfg_attr(pwr_g0, path = "g0.rs")]
#[cfg_attr(pwr_l1, path = "l1.rs")]
mod _version; mod _version;
pub use _version::*; pub use _version::*;

43
embassy-stm32/src/rcc/l1/mod.rs
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@ -7,7 +7,6 @@ use crate::time::U32Ext;
use core::marker::PhantomData; use core::marker::PhantomData;
use embassy::util::Unborrow; use embassy::util::Unborrow;
use embassy_hal_common::unborrow; use embassy_hal_common::unborrow;
use pac::rcc::vals::{Hpre, Ppre, Sw};
/// Most of clock setup is copied from rcc/l0 /// Most of clock setup is copied from rcc/l0
@ -22,30 +21,32 @@ pub enum ClockSrc {
HSI, HSI,
} }
type Ppre = u8;
impl Into<Ppre> for APBPrescaler { impl Into<Ppre> for APBPrescaler {
fn into(self) -> Ppre { fn into(self) -> Ppre {
match self { match self {
APBPrescaler::NotDivided => Ppre::DIV1, APBPrescaler::NotDivided => 0b000,
APBPrescaler::Div2 => Ppre::DIV2, APBPrescaler::Div2 => 0b100,
APBPrescaler::Div4 => Ppre::DIV4, APBPrescaler::Div4 => 0b101,
APBPrescaler::Div8 => Ppre::DIV8, APBPrescaler::Div8 => 0b110,
APBPrescaler::Div16 => Ppre::DIV16, APBPrescaler::Div16 => 0b111,
} }
} }
} }
type Hpre = u8;
impl Into<Hpre> for AHBPrescaler { impl Into<Hpre> for AHBPrescaler {
fn into(self) -> Hpre { fn into(self) -> Hpre {
match self { match self {
AHBPrescaler::NotDivided => Hpre::DIV1, AHBPrescaler::NotDivided => 0b0000,
AHBPrescaler::Div2 => Hpre::DIV2, AHBPrescaler::Div2 => 0b1000,
AHBPrescaler::Div4 => Hpre::DIV4, AHBPrescaler::Div4 => 0b1001,
AHBPrescaler::Div8 => Hpre::DIV8, AHBPrescaler::Div8 => 0b1010,
AHBPrescaler::Div16 => Hpre::DIV16, AHBPrescaler::Div16 => 0b1011,
AHBPrescaler::Div64 => Hpre::DIV64, AHBPrescaler::Div64 => 0b1100,
AHBPrescaler::Div128 => Hpre::DIV128, AHBPrescaler::Div128 => 0b1101,
AHBPrescaler::Div256 => Hpre::DIV256, AHBPrescaler::Div256 => 0b1110,
AHBPrescaler::Div512 => Hpre::DIV512, AHBPrescaler::Div512 => 0b1111,
} }
} }
} }
@ -157,7 +158,7 @@ impl RccExt for RCC {
} }
let freq = 32_768 * (1 << (range as u8 + 1)); let freq = 32_768 * (1 << (range as u8 + 1));
(freq, Sw::MSI) (freq, 0b00)
} }
ClockSrc::HSI => { ClockSrc::HSI => {
// Enable HSI // Enable HSI
@ -166,7 +167,7 @@ impl RccExt for RCC {
while !rcc.cr().read().hsirdy() {} while !rcc.cr().read().hsirdy() {}
} }
(HSI_FREQ, Sw::HSI) (HSI_FREQ, 0b01)
} }
ClockSrc::HSE(freq) => { ClockSrc::HSE(freq) => {
// Enable HSE // Enable HSE
@ -175,7 +176,7 @@ impl RccExt for RCC {
while !rcc.cr().read().hserdy() {} while !rcc.cr().read().hserdy() {}
} }
(freq.0, Sw::HSE) (freq.0, 0b10)
} }
}; };
@ -192,7 +193,7 @@ impl RccExt for RCC {
AHBPrescaler::NotDivided => sys_clk, AHBPrescaler::NotDivided => sys_clk,
pre => { pre => {
let pre: Hpre = pre.into(); let pre: Hpre = pre.into();
let pre = 1 << (pre.0 as u32 - 7); let pre = 1 << (pre as u32 - 7);
sys_clk / pre sys_clk / pre
} }
}; };
@ -201,7 +202,7 @@ impl RccExt for RCC {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq), APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => { pre => {
let pre: Ppre = pre.into(); let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.0 - 3); let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / pre as u32; let freq = ahb_freq / pre as u32;
(freq, freq * 2) (freq, freq * 2)
} }
@ -211,7 +212,7 @@ impl RccExt for RCC {
APBPrescaler::NotDivided => (ahb_freq, ahb_freq), APBPrescaler::NotDivided => (ahb_freq, ahb_freq),
pre => { pre => {
let pre: Ppre = pre.into(); let pre: Ppre = pre.into();
let pre: u8 = 1 << (pre.0 - 3); let pre: u8 = 1 << (pre - 3);
let freq = ahb_freq / (1 << (pre as u8 - 3)); let freq = ahb_freq / (1 << (pre as u8 - 3));
(freq, freq * 2) (freq, freq * 2)
} }

2
stm32-data

@ -1 +1 @@
Subproject commit 7f5f8e7c641d74a0e97e2d84bac61b7c6c267a7e Subproject commit 18df82005f29da14e7d4c442f7cff3a46939c434