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stm32/rcc: use AHBPrescaler div impls in stm32wba

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This commit is contained in:
Dario Nieuwenhuis 2023-09-17 02:30:50 +02:00
parent 3ddc9cd110
commit bbe1d96045
3 changed files with 33 additions and 60 deletions
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4
embassy-stm32/src/rcc/bus.rs
View File

@ -41,9 +41,13 @@ impl Div<AHBPrescaler> for Hertz {
AHBPrescaler::DIV16 => 16,
#[cfg(any(rcc_wb, rcc_wl5, rcc_wle))]
AHBPrescaler::DIV32 => 32,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV64 => 64,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV128 => 128,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV256 => 256,
#[cfg(not(rcc_wba))]
AHBPrescaler::DIV512 => 512,
_ => unreachable!(),
};

1
embassy-stm32/src/rcc/mod.rs
View File

@ -1,7 +1,6 @@
#![macro_use]
pub(crate) mod bd;
#[cfg(not(rcc_wba))]
pub mod bus;
use core::mem::MaybeUninit;

88
embassy-stm32/src/rcc/wba.rs
View File

@ -43,36 +43,6 @@ impl Into<Sw> for ClockSrc {
}
}
trait Div {
fn div(&self) -> u8;
}
impl Div for APBPrescaler {
fn div(&self) -> u8 {
match self {
Self::DIV1 => 1,
Self::DIV2 => 2,
Self::DIV4 => 4,
Self::DIV8 => 8,
Self::DIV16 => 16,
_ => unreachable!(),
}
}
}
impl Div for AHBPrescaler {
fn div(&self) -> u8 {
match self {
Self::DIV1 => 1,
Self::DIV2 => 2,
Self::DIV4 => 4,
Self::DIV8 => 8,
Self::DIV16 => 16,
_ => unreachable!(),
}
}
}
#[derive(Copy, Clone)]
pub struct Config {
pub mux: ClockSrc,
@ -100,13 +70,13 @@ pub(crate) unsafe fn init(config: Config) {
RCC.cr().write(|w| w.set_hseon(true));
while !RCC.cr().read().hserdy() {}
freq.0
freq
}
ClockSrc::HSI16 => {
RCC.cr().write(|w| w.set_hsion(true));
while !RCC.cr().read().hsirdy() {}
HSI_FREQ.0
HSI_FREQ
}
};
@ -115,14 +85,14 @@ pub(crate) unsafe fn init(config: Config) {
// states and programming delay
let wait_states = match power_vos {
VoltageScale::RANGE1 => match sys_clk {
VoltageScale::RANGE1 => match sys_clk.0 {
..=32_000_000 => 0,
..=64_000_000 => 1,
..=96_000_000 => 2,
..=100_000_000 => 3,
_ => 4,
},
VoltageScale::RANGE2 => match sys_clk {
VoltageScale::RANGE2 => match sys_clk.0 {
..=8_000_000 => 0,
..=16_000_000 => 1,
_ => 2,
@ -147,38 +117,38 @@ pub(crate) unsafe fn init(config: Config) {
w.set_ppre7(config.apb7_pre.into());
});
let ahb_freq: u32 = sys_clk / config.ahb_pre.div() as u32;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre.div() {
1 => (ahb_freq, ahb_freq),
div => {
let freq = ahb_freq / div as u32;
(freq, freq * 2)
let ahb_freq = sys_clk / config.ahb_pre;
let (apb1_freq, apb1_tim_freq) = match config.apb1_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre.div() {
1 => (ahb_freq, ahb_freq),
div => {
let freq = ahb_freq / div as u32;
(freq, freq * 2)
let (apb2_freq, apb2_tim_freq) = match config.apb2_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
let (apb7_freq, _apb7_tim_freq) = match config.apb7_pre.div() {
1 => (ahb_freq, ahb_freq),
div => {
let freq = ahb_freq / div as u32;
(freq, freq * 2)
let (apb7_freq, _apb7_tim_freq) = match config.apb7_pre {
APBPrescaler::DIV1 => (ahb_freq, ahb_freq),
pre => {
let freq = ahb_freq / pre;
(freq, freq * 2u32)
}
};
set_freqs(Clocks {
sys: Hertz(sys_clk),
ahb1: Hertz(ahb_freq),
ahb2: Hertz(ahb_freq),
ahb4: Hertz(ahb_freq),
apb1: Hertz(apb1_freq),
apb2: Hertz(apb2_freq),
apb7: Hertz(apb7_freq),
apb1_tim: Hertz(apb1_tim_freq),
apb2_tim: Hertz(apb2_tim_freq),
sys: sys_clk,
ahb1: ahb_freq,
ahb2: ahb_freq,
ahb4: ahb_freq,
apb1: apb1_freq,
apb2: apb2_freq,
apb7: apb7_freq,
apb1_tim: apb1_tim_freq,
apb2_tim: apb2_tim_freq,
});
}