stm32/i2c: add async, dual interrupt scaffolding.
This commit is contained in:
parent
e8ff5a2baf
commit
bc65b8f7ec
@ -58,7 +58,7 @@ rand_core = "0.6.3"
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sdio-host = "0.5.0"
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sdio-host = "0.5.0"
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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embedded-sdmmc = { git = "https://github.com/embassy-rs/embedded-sdmmc-rs", rev = "a4f293d3a6f72158385f79c98634cb8a14d0d2fc", optional = true }
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critical-section = "1.1"
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critical-section = "1.1"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fbb8f77326dd066aa6c0d66b3b46e76a569dda8b" }
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f6d1ffc1a25f208b5cd6b1024bff246592da1949" }
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vcell = "0.1.3"
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vcell = "0.1.3"
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bxcan = "0.7.0"
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bxcan = "0.7.0"
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nb = "1.0.0"
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nb = "1.0.0"
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@ -76,7 +76,7 @@ critical-section = { version = "1.1", features = ["std"] }
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[build-dependencies]
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[build-dependencies]
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proc-macro2 = "1.0.36"
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proc-macro2 = "1.0.36"
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quote = "1.0.15"
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quote = "1.0.15"
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-fbb8f77326dd066aa6c0d66b3b46e76a569dda8b", default-features = false, features = ["metadata"]}
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stm32-metapac = { git = "https://github.com/embassy-rs/stm32-data-generated", tag = "stm32-data-f6d1ffc1a25f208b5cd6b1024bff246592da1949", default-features = false, features = ["metadata"]}
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[features]
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[features]
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@ -1138,6 +1138,23 @@ fn main() {
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}
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}
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}
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}
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// ========
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// Write peripheral_interrupts module.
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let mut mt = TokenStream::new();
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for p in METADATA.peripherals {
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let mut pt = TokenStream::new();
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for irq in p.interrupts {
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let iname = format_ident!("{}", irq.interrupt);
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let sname = format_ident!("{}", irq.signal);
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pt.extend(quote!(pub type #sname = crate::interrupt::typelevel::#iname;));
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}
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let pname = format_ident!("{}", p.name);
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mt.extend(quote!(pub mod #pname { #pt }));
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}
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g.extend(quote!(#[allow(non_camel_case_types)] pub mod peripheral_interrupts { #mt }));
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// ========
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// ========
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// Write foreach_foo! macrotables
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// Write foreach_foo! macrotables
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@ -1296,6 +1313,9 @@ fn main() {
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let mut m = String::new();
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let mut m = String::new();
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// DO NOT ADD more macros like these.
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// These turned to be a bad idea!
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// Instead, make build.rs generate the final code.
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make_table(&mut m, "foreach_flash_region", &flash_regions_table);
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make_table(&mut m, "foreach_flash_region", &flash_regions_table);
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make_table(&mut m, "foreach_interrupt", &interrupts_table);
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make_table(&mut m, "foreach_interrupt", &interrupts_table);
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make_table(&mut m, "foreach_peripheral", &peripherals_table);
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make_table(&mut m, "foreach_peripheral", &peripherals_table);
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@ -1,11 +1,14 @@
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#![macro_use]
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#![macro_use]
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use core::marker::PhantomData;
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use crate::interrupt;
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use crate::interrupt;
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#[cfg_attr(i2c_v1, path = "v1.rs")]
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#[cfg_attr(i2c_v1, path = "v1.rs")]
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#[cfg_attr(i2c_v2, path = "v2.rs")]
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#[cfg_attr(i2c_v2, path = "v2.rs")]
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mod _version;
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mod _version;
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pub use _version::*;
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pub use _version::*;
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use embassy_sync::waitqueue::AtomicWaker;
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use crate::peripherals;
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use crate::peripherals;
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@ -23,6 +26,20 @@ pub enum Error {
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pub(crate) mod sealed {
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pub(crate) mod sealed {
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use super::*;
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use super::*;
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pub struct State {
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#[allow(unused)]
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pub waker: AtomicWaker,
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}
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impl State {
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pub const fn new() -> Self {
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Self {
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waker: AtomicWaker::new(),
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}
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}
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}
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pub trait Instance: crate::rcc::RccPeripheral {
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pub trait Instance: crate::rcc::RccPeripheral {
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fn regs() -> crate::pac::i2c::I2c;
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fn regs() -> crate::pac::i2c::I2c;
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fn state() -> &'static State;
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fn state() -> &'static State;
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@ -30,7 +47,8 @@ pub(crate) mod sealed {
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}
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}
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pub trait Instance: sealed::Instance + 'static {
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pub trait Instance: sealed::Instance + 'static {
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type Interrupt: interrupt::typelevel::Interrupt;
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type EventInterrupt: interrupt::typelevel::Interrupt;
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type ErrorInterrupt: interrupt::typelevel::Interrupt;
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}
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}
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pin_trait!(SclPin, Instance);
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pin_trait!(SclPin, Instance);
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@ -38,21 +56,148 @@ pin_trait!(SdaPin, Instance);
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dma_trait!(RxDma, Instance);
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dma_trait!(RxDma, Instance);
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dma_trait!(TxDma, Instance);
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dma_trait!(TxDma, Instance);
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foreach_interrupt!(
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/// Interrupt handler.
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($inst:ident, i2c, $block:ident, EV, $irq:ident) => {
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pub struct EventInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::EventInterrupt> for EventInterruptHandler<T> {
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unsafe fn on_interrupt() {
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_version::on_interrupt::<T>()
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}
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}
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pub struct ErrorInterruptHandler<T: Instance> {
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::ErrorInterrupt> for ErrorInterruptHandler<T> {
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unsafe fn on_interrupt() {
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_version::on_interrupt::<T>()
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}
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}
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foreach_peripheral!(
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(i2c, $inst:ident) => {
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impl sealed::Instance for peripherals::$inst {
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impl sealed::Instance for peripherals::$inst {
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fn regs() -> crate::pac::i2c::I2c {
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fn regs() -> crate::pac::i2c::I2c {
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crate::pac::$inst
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crate::pac::$inst
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}
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}
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fn state() -> &'static State {
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fn state() -> &'static sealed::State {
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static STATE: State = State::new();
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static STATE: sealed::State = sealed::State::new();
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&STATE
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&STATE
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}
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}
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}
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}
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impl Instance for peripherals::$inst {
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impl Instance for peripherals::$inst {
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type Interrupt = crate::interrupt::typelevel::$irq;
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type EventInterrupt = crate::_generated::peripheral_interrupts::$inst::EV;
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type ErrorInterrupt = crate::_generated::peripheral_interrupts::$inst::ER;
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}
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}
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};
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};
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);
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);
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mod eh02 {
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use super::*;
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
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type Error = Error;
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fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(address, buffer)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
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type Error = Error;
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fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(address, write)
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}
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}
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impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
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type Error = Error;
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fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_write_read(address, write, read)
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}
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}
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}
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#[cfg(feature = "unstable-traits")]
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mod eh1 {
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use super::*;
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use crate::dma::NoDma;
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impl embedded_hal_1::i2c::Error for Error {
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fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
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match *self {
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Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
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Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
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Self::Nack => {
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embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
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}
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Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
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Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
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Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
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Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
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}
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}
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}
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impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
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type Error = Error;
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}
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impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, NoDma, NoDma> {
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fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_read(address, read)
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}
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fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
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self.blocking_write(address, write)
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}
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fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
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self.blocking_write_read(address, write, read)
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}
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fn transaction(
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&mut self,
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_address: u8,
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_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
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) -> Result<(), Self::Error> {
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todo!();
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}
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}
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}
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#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
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mod eha {
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use super::*;
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impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
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async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
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self.read(address, read).await
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}
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async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
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self.write(address, write).await
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}
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async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
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self.write_read(address, write, read).await
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}
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async fn transaction(
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&mut self,
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address: u8,
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operations: &mut [embedded_hal_1::i2c::Operation<'_>],
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) -> Result<(), Self::Error> {
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let _ = address;
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let _ = operations;
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todo!()
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}
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}
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}
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@ -3,21 +3,17 @@ use core::marker::PhantomData;
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use embassy_embedded_hal::SetConfig;
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use embassy_embedded_hal::SetConfig;
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use embassy_hal_internal::{into_ref, PeripheralRef};
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use super::*;
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use crate::dma::NoDma;
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use crate::dma::NoDma;
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use crate::gpio::sealed::AFType;
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use crate::gpio::sealed::AFType;
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use crate::gpio::Pull;
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use crate::gpio::Pull;
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use crate::i2c::{Error, Instance, SclPin, SdaPin};
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use crate::interrupt::typelevel::Interrupt;
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use crate::pac::i2c;
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use crate::pac::i2c;
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use crate::time::Hertz;
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use crate::time::Hertz;
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use crate::{interrupt, Peripheral};
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use crate::{interrupt, Peripheral};
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/// Interrupt handler.
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pub unsafe fn on_interrupt<T: Instance>() {
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pub struct InterruptHandler<T: Instance> {
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// todo
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_phantom: PhantomData<T>,
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}
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impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
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unsafe fn on_interrupt() {}
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}
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}
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#[non_exhaustive]
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#[non_exhaustive]
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@ -27,14 +23,6 @@ pub struct Config {
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pub scl_pullup: bool,
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pub scl_pullup: bool,
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}
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}
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pub struct State {}
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impl State {
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pub(crate) const fn new() -> Self {
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Self {}
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}
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}
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
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phantom: PhantomData<&'d mut T>,
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phantom: PhantomData<&'d mut T>,
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#[allow(dead_code)]
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#[allow(dead_code)]
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@ -48,7 +36,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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_peri: impl Peripheral<P = T> + 'd,
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_peri: impl Peripheral<P = T> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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scl: impl Peripheral<P = impl SclPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
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_irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
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+ interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
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+ 'd,
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tx_dma: impl Peripheral<P = TXDMA> + 'd,
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tx_dma: impl Peripheral<P = TXDMA> + 'd,
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rx_dma: impl Peripheral<P = RXDMA> + 'd,
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rx_dma: impl Peripheral<P = RXDMA> + 'd,
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freq: Hertz,
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freq: Hertz,
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@ -98,6 +88,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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reg.set_pe(true);
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reg.set_pe(true);
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});
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});
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unsafe { T::EventInterrupt::enable() };
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unsafe { T::ErrorInterrupt::enable() };
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Self {
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Self {
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phantom: PhantomData,
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phantom: PhantomData,
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tx_dma,
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tx_dma,
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@ -336,6 +329,30 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
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pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
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pub fn blocking_write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Error> {
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self.blocking_write_read_timeout(addr, write, read, || Ok(()))
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self.blocking_write_read_timeout(addr, write, read, || Ok(()))
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}
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}
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// Async
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pub async fn write(&mut self, _address: u8, _write: &[u8]) -> Result<(), Error>
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where
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||||||
|
TXDMA: crate::i2c::TxDma<T>,
|
||||||
|
{
|
||||||
|
todo!()
|
||||||
|
}
|
||||||
|
|
||||||
|
pub async fn read(&mut self, _address: u8, _buffer: &mut [u8]) -> Result<(), Error>
|
||||||
|
where
|
||||||
|
RXDMA: crate::i2c::RxDma<T>,
|
||||||
|
{
|
||||||
|
todo!()
|
||||||
|
}
|
||||||
|
|
||||||
|
pub async fn write_read(&mut self, _address: u8, _write: &[u8], _read: &mut [u8]) -> Result<(), Error>
|
||||||
|
where
|
||||||
|
RXDMA: crate::i2c::RxDma<T>,
|
||||||
|
TXDMA: crate::i2c::TxDma<T>,
|
||||||
|
{
|
||||||
|
todo!()
|
||||||
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
|
impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
|
||||||
@ -344,77 +361,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn read(&mut self, addr: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_read(addr, read)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn write(&mut self, addr: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write(addr, write)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn write_read(&mut self, addr: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write_read(addr, write, read)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#[cfg(feature = "unstable-traits")]
|
|
||||||
mod eh1 {
|
|
||||||
use super::*;
|
|
||||||
|
|
||||||
impl embedded_hal_1::i2c::Error for Error {
|
|
||||||
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
|
|
||||||
match *self {
|
|
||||||
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
|
|
||||||
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
|
|
||||||
Self::Nack => {
|
|
||||||
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
|
|
||||||
}
|
|
||||||
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
|
|
||||||
Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_1::i2c::ErrorType for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T> {
|
|
||||||
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_read(address, read)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write(address, write)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write_read(address, write, read)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn transaction(
|
|
||||||
&mut self,
|
|
||||||
_address: u8,
|
|
||||||
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
|
|
||||||
) -> Result<(), Self::Error> {
|
|
||||||
todo!();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
enum Mode {
|
enum Mode {
|
||||||
Fast,
|
Fast,
|
||||||
Standard,
|
Standard,
|
||||||
|
@ -1,19 +1,17 @@
|
|||||||
use core::cmp;
|
use core::cmp;
|
||||||
use core::future::poll_fn;
|
use core::future::poll_fn;
|
||||||
use core::marker::PhantomData;
|
|
||||||
use core::task::Poll;
|
use core::task::Poll;
|
||||||
|
|
||||||
use embassy_embedded_hal::SetConfig;
|
use embassy_embedded_hal::SetConfig;
|
||||||
use embassy_hal_internal::drop::OnDrop;
|
use embassy_hal_internal::drop::OnDrop;
|
||||||
use embassy_hal_internal::{into_ref, PeripheralRef};
|
use embassy_hal_internal::{into_ref, PeripheralRef};
|
||||||
use embassy_sync::waitqueue::AtomicWaker;
|
|
||||||
#[cfg(feature = "time")]
|
#[cfg(feature = "time")]
|
||||||
use embassy_time::{Duration, Instant};
|
use embassy_time::{Duration, Instant};
|
||||||
|
|
||||||
|
use super::*;
|
||||||
use crate::dma::{NoDma, Transfer};
|
use crate::dma::{NoDma, Transfer};
|
||||||
use crate::gpio::sealed::AFType;
|
use crate::gpio::sealed::AFType;
|
||||||
use crate::gpio::Pull;
|
use crate::gpio::Pull;
|
||||||
use crate::i2c::{Error, Instance, SclPin, SdaPin};
|
|
||||||
use crate::interrupt::typelevel::Interrupt;
|
use crate::interrupt::typelevel::Interrupt;
|
||||||
use crate::pac::i2c;
|
use crate::pac::i2c;
|
||||||
use crate::time::Hertz;
|
use crate::time::Hertz;
|
||||||
@ -36,13 +34,7 @@ pub fn no_timeout_fn() -> impl Fn() -> Result<(), Error> {
|
|||||||
move || Ok(())
|
move || Ok(())
|
||||||
}
|
}
|
||||||
|
|
||||||
/// Interrupt handler.
|
pub unsafe fn on_interrupt<T: Instance>() {
|
||||||
pub struct InterruptHandler<T: Instance> {
|
|
||||||
_phantom: PhantomData<T>,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandler<T> {
|
|
||||||
unsafe fn on_interrupt() {
|
|
||||||
let regs = T::regs();
|
let regs = T::regs();
|
||||||
let isr = regs.isr().read();
|
let isr = regs.isr().read();
|
||||||
|
|
||||||
@ -55,7 +47,6 @@ impl<T: Instance> interrupt::typelevel::Handler<T::Interrupt> for InterruptHandl
|
|||||||
regs.cr1().modify(|w| w.set_tcie(false));
|
regs.cr1().modify(|w| w.set_tcie(false));
|
||||||
});
|
});
|
||||||
}
|
}
|
||||||
}
|
|
||||||
|
|
||||||
#[non_exhaustive]
|
#[non_exhaustive]
|
||||||
#[derive(Copy, Clone)]
|
#[derive(Copy, Clone)]
|
||||||
@ -77,18 +68,6 @@ impl Default for Config {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
pub struct State {
|
|
||||||
waker: AtomicWaker,
|
|
||||||
}
|
|
||||||
|
|
||||||
impl State {
|
|
||||||
pub(crate) const fn new() -> Self {
|
|
||||||
Self {
|
|
||||||
waker: AtomicWaker::new(),
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
|
pub struct I2c<'d, T: Instance, TXDMA = NoDma, RXDMA = NoDma> {
|
||||||
_peri: PeripheralRef<'d, T>,
|
_peri: PeripheralRef<'d, T>,
|
||||||
#[allow(dead_code)]
|
#[allow(dead_code)]
|
||||||
@ -104,7 +83,9 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
|||||||
peri: impl Peripheral<P = T> + 'd,
|
peri: impl Peripheral<P = T> + 'd,
|
||||||
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
|
scl: impl Peripheral<P = impl SclPin<T>> + 'd,
|
||||||
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
|
sda: impl Peripheral<P = impl SdaPin<T>> + 'd,
|
||||||
_irq: impl interrupt::typelevel::Binding<T::Interrupt, InterruptHandler<T>> + 'd,
|
_irq: impl interrupt::typelevel::Binding<T::EventInterrupt, EventInterruptHandler<T>>
|
||||||
|
+ interrupt::typelevel::Binding<T::ErrorInterrupt, ErrorInterruptHandler<T>>
|
||||||
|
+ 'd,
|
||||||
tx_dma: impl Peripheral<P = TXDMA> + 'd,
|
tx_dma: impl Peripheral<P = TXDMA> + 'd,
|
||||||
rx_dma: impl Peripheral<P = RXDMA> + 'd,
|
rx_dma: impl Peripheral<P = RXDMA> + 'd,
|
||||||
freq: Hertz,
|
freq: Hertz,
|
||||||
@ -150,8 +131,8 @@ impl<'d, T: Instance, TXDMA, RXDMA> I2c<'d, T, TXDMA, RXDMA> {
|
|||||||
reg.set_pe(true);
|
reg.set_pe(true);
|
||||||
});
|
});
|
||||||
|
|
||||||
T::Interrupt::unpend();
|
unsafe { T::EventInterrupt::enable() };
|
||||||
unsafe { T::Interrupt::enable() };
|
unsafe { T::ErrorInterrupt::enable() };
|
||||||
|
|
||||||
Self {
|
Self {
|
||||||
_peri: peri,
|
_peri: peri,
|
||||||
@ -987,35 +968,6 @@ impl<'d, T: Instance, TXDMA, RXDMA> Drop for I2c<'d, T, TXDMA, RXDMA> {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[cfg(feature = "time")]
|
|
||||||
mod eh02 {
|
|
||||||
use super::*;
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Read for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn read(&mut self, address: u8, buffer: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_read(address, buffer)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::Write for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write(address, write)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_02::blocking::i2c::WriteRead for I2c<'d, T> {
|
|
||||||
type Error = Error;
|
|
||||||
|
|
||||||
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write_read(address, write, read)
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
/// I2C Stop Configuration
|
/// I2C Stop Configuration
|
||||||
///
|
///
|
||||||
/// Peripheral options for generating the STOP condition
|
/// Peripheral options for generating the STOP condition
|
||||||
@ -1140,83 +1092,6 @@ impl Timings {
|
|||||||
}
|
}
|
||||||
}
|
}
|
||||||
|
|
||||||
#[cfg(feature = "unstable-traits")]
|
|
||||||
mod eh1 {
|
|
||||||
use super::*;
|
|
||||||
|
|
||||||
impl embedded_hal_1::i2c::Error for Error {
|
|
||||||
fn kind(&self) -> embedded_hal_1::i2c::ErrorKind {
|
|
||||||
match *self {
|
|
||||||
Self::Bus => embedded_hal_1::i2c::ErrorKind::Bus,
|
|
||||||
Self::Arbitration => embedded_hal_1::i2c::ErrorKind::ArbitrationLoss,
|
|
||||||
Self::Nack => {
|
|
||||||
embedded_hal_1::i2c::ErrorKind::NoAcknowledge(embedded_hal_1::i2c::NoAcknowledgeSource::Unknown)
|
|
||||||
}
|
|
||||||
Self::Timeout => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
Self::Crc => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
Self::Overrun => embedded_hal_1::i2c::ErrorKind::Overrun,
|
|
||||||
Self::ZeroLengthTransfer => embedded_hal_1::i2c::ErrorKind::Other,
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance, TXDMA, RXDMA> embedded_hal_1::i2c::ErrorType for I2c<'d, T, TXDMA, RXDMA> {
|
|
||||||
type Error = Error;
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> embedded_hal_1::i2c::I2c for I2c<'d, T, NoDma, NoDma> {
|
|
||||||
fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_read(address, read)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write(address, write)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.blocking_write_read(address, write, read)
|
|
||||||
}
|
|
||||||
|
|
||||||
fn transaction(
|
|
||||||
&mut self,
|
|
||||||
_address: u8,
|
|
||||||
_operations: &mut [embedded_hal_1::i2c::Operation<'_>],
|
|
||||||
) -> Result<(), Self::Error> {
|
|
||||||
todo!();
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
#[cfg(all(feature = "unstable-traits", feature = "nightly"))]
|
|
||||||
mod eha {
|
|
||||||
use super::super::{RxDma, TxDma};
|
|
||||||
use super::*;
|
|
||||||
|
|
||||||
impl<'d, T: Instance, TXDMA: TxDma<T>, RXDMA: RxDma<T>> embedded_hal_async::i2c::I2c for I2c<'d, T, TXDMA, RXDMA> {
|
|
||||||
async fn read(&mut self, address: u8, read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.read(address, read).await
|
|
||||||
}
|
|
||||||
|
|
||||||
async fn write(&mut self, address: u8, write: &[u8]) -> Result<(), Self::Error> {
|
|
||||||
self.write(address, write).await
|
|
||||||
}
|
|
||||||
|
|
||||||
async fn write_read(&mut self, address: u8, write: &[u8], read: &mut [u8]) -> Result<(), Self::Error> {
|
|
||||||
self.write_read(address, write, read).await
|
|
||||||
}
|
|
||||||
|
|
||||||
async fn transaction(
|
|
||||||
&mut self,
|
|
||||||
address: u8,
|
|
||||||
operations: &mut [embedded_hal_1::i2c::Operation<'_>],
|
|
||||||
) -> Result<(), Self::Error> {
|
|
||||||
let _ = address;
|
|
||||||
let _ = operations;
|
|
||||||
todo!()
|
|
||||||
}
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
impl<'d, T: Instance> SetConfig for I2c<'d, T> {
|
impl<'d, T: Instance> SetConfig for I2c<'d, T> {
|
||||||
type Config = Hertz;
|
type Config = Hertz;
|
||||||
type ConfigError = ();
|
type ConfigError = ();
|
||||||
|
@ -14,7 +14,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -13,7 +13,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -19,7 +19,8 @@ const HEIGHT: usize = 100;
|
|||||||
static mut FRAME: [u32; WIDTH * HEIGHT / 2] = [0u32; WIDTH * HEIGHT / 2];
|
static mut FRAME: [u32; WIDTH * HEIGHT / 2] = [0u32; WIDTH * HEIGHT / 2];
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C1_EV => i2c::InterruptHandler<peripherals::I2C1>;
|
I2C1_EV => i2c::EventInterruptHandler<peripherals::I2C1>;
|
||||||
|
I2C1_ER => i2c::ErrorInterruptHandler<peripherals::I2C1>;
|
||||||
DCMI => dcmi::InterruptHandler<peripherals::DCMI>;
|
DCMI => dcmi::InterruptHandler<peripherals::DCMI>;
|
||||||
});
|
});
|
||||||
|
|
||||||
|
@ -13,7 +13,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -14,7 +14,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -16,7 +16,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -13,7 +13,8 @@ const ADDRESS: u8 = 0x5F;
|
|||||||
const WHOAMI: u8 = 0x0F;
|
const WHOAMI: u8 = 0x0F;
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C2_EV => i2c::InterruptHandler<peripherals::I2C2>;
|
I2C2_EV => i2c::EventInterruptHandler<peripherals::I2C2>;
|
||||||
|
I2C2_ER => i2c::ErrorInterruptHandler<peripherals::I2C2>;
|
||||||
});
|
});
|
||||||
|
|
||||||
#[embassy_executor::main]
|
#[embassy_executor::main]
|
||||||
|
@ -40,7 +40,8 @@ use static_cell::make_static;
|
|||||||
use {embassy_stm32 as hal, panic_probe as _};
|
use {embassy_stm32 as hal, panic_probe as _};
|
||||||
|
|
||||||
bind_interrupts!(struct Irqs {
|
bind_interrupts!(struct Irqs {
|
||||||
I2C3_EV => i2c::InterruptHandler<peripherals::I2C3>;
|
I2C3_EV => i2c::EventInterruptHandler<peripherals::I2C3>;
|
||||||
|
I2C3_ER => i2c::ErrorInterruptHandler<peripherals::I2C3>;
|
||||||
RNG => rng::InterruptHandler<peripherals::RNG>;
|
RNG => rng::InterruptHandler<peripherals::RNG>;
|
||||||
});
|
});
|
||||||
|
|
||||||
|
Loading…
Reference in New Issue
Block a user