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Merge pull request #228 from embassy-rs/metapac2

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stm32-metapac: add new codegen, allows pregenerating the entire pac
This commit is contained in:
Dario Nieuwenhuis 2021-06-10 03:49:41 +02:00 committed by GitHub
commit bd7425a571
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GPG Key ID: 4AEE18F83AFDEB23
11 changed files with 562 additions and 375 deletions
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12
.github/workflows/rust.yml vendored
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@ -112,3 +112,15 @@ jobs:
toolchain: stable
- name: Check fmt
run: for i in embassy-*; do (cd $i; cargo fmt -- --check); done
metapac_gen:
runs-on: ubuntu-latest
steps:
- uses: actions/checkout@v2
with:
submodules: true
- uses: actions-rs/toolchain@v1
with:
toolchain: stable
- name: Generate pregenerated metapac
run: cd stm32-metapac/gen; cargo run --release

2
stm32-data

@ -1 +1 @@
Subproject commit f07c793bbe81b01b2f3668177648f024ec1c8fb1
Subproject commit 679a1e238835ac67597c6327cc6fb7e29bec0957

5
stm32-metapac/Cargo.toml
View File

@ -11,10 +11,7 @@ cortex-m-rt = { version = "0.6.8", optional = true }
# BEGIN BUILD DEPENDENCIES
# These are removed when generating the pre-generated crate using the tool at gen/.
[build-dependencies]
regex = "1.4.6"
chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "86b77165078065058098e981d49d2dd213b2feba" }
serde = { version = "1.0.123", features = [ "derive" ]}
serde_yaml = "0.8.15"
stm32-metapac-gen = { path = "./gen" }
# END BUILD DEPENDENCIES
[features]

380
stm32-metapac/build.rs
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@ -1,136 +1,10 @@
use regex::Regex;
use serde::Deserialize;
use std::collections::{HashMap, HashSet};
use std::env;
use std::fmt::Write as _;
use std::fs;
use std::fs::File;
use std::io::Write;
use std::path::Path;
use std::path::PathBuf;
use chiptool::{generate, ir, transform};
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Chip {
pub name: String,
pub family: String,
pub line: String,
pub core: String,
pub flash: u32,
pub ram: u32,
pub gpio_af: String,
pub packages: Vec<Package>,
pub peripherals: HashMap<String, Peripheral>,
pub interrupts: HashMap<String, u32>,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Package {
pub name: String,
pub package: String,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Peripheral {
pub address: u32,
#[serde(default)]
pub kind: Option<String>,
#[serde(default)]
pub block: Option<String>,
#[serde(default)]
pub clock: Option<String>,
#[serde(default)]
pub pins: Vec<Pin>,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Pin {
pub pin: String,
pub signal: String,
pub af: Option<String>,
}
struct BlockInfo {
/// usart_v1/USART -> usart
module: String,
/// usart_v1/USART -> v1
version: String,
/// usart_v1/USART -> USART
block: String,
}
impl BlockInfo {
fn parse(s: &str) -> Self {
let mut s = s.split("/");
let module = s.next().unwrap();
let block = s.next().unwrap();
assert!(s.next().is_none());
let mut s = module.split("_");
let module = s.next().unwrap();
let version = s.next().unwrap();
assert!(s.next().is_none());
Self {
module: module.to_string(),
version: version.to_string(),
block: block.to_string(),
}
}
}
fn make_table(out: &mut String, name: &str, data: &Vec<Vec<String>>) {
write!(
out,
"#[macro_export]
macro_rules! {} {{
($($pat:tt => $code:tt;)*) => {{
macro_rules! __{}_inner {{
$(($pat) => $code;)*
($_:tt) => {{}}
}}
",
name, name
)
.unwrap();
for row in data {
write!(out, " __{}_inner!(({}));\n", name, row.join(",")).unwrap();
}
write!(
out,
" }};
}}"
)
.unwrap();
}
fn find_reg_for_field<'c>(
rcc: &'c ir::IR,
reg_prefix: &str,
field_name: &str,
) -> Option<(&'c str, &'c str)> {
rcc.fieldsets.iter().find_map(|(name, fieldset)| {
if name.starts_with(reg_prefix) {
fieldset
.fields
.iter()
.find_map(|field| {
if field_name == field.name {
return Some(field.name.as_str());
} else {
None
}
})
.map(|n| (name.as_str(), n))
} else {
None
}
})
}
use stm32_metapac_gen::*;
fn main() {
let dir = "../stm32-data/data";
let out_dir = PathBuf::from(env::var_os("OUT_DIR").unwrap());
let data_dir = PathBuf::from("../stm32-data/data");
println!("cwd: {:?}", env::current_dir());
@ -142,248 +16,16 @@ fn main() {
.unwrap()
.to_ascii_uppercase();
let chip_path = Path::new(&dir)
.join("chips")
.join(&format!("{}.yaml", chip_name));
let chip = fs::read(chip_path).unwrap();
let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
let mut ir = ir::IR::new();
let mut dev = ir::Device {
interrupts: Vec::new(),
peripherals: Vec::new(),
};
// Load RCC register for chip
let rcc = chip.peripherals.iter().find_map(|(name, p)| {
if name == "RCC" {
p.block.as_ref().map(|block| {
let bi = BlockInfo::parse(block);
let rcc_reg_path = Path::new(&dir)
.join("registers")
.join(&format!("{}_{}.yaml", bi.module, bi.version));
serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap()
})
} else {
None
}
gen(Options {
out_dir: out_dir.clone(),
data_dir: data_dir.clone(),
chips: vec![chip_name.clone()],
});
let mut peripheral_versions: HashMap<String, String> = HashMap::new();
let mut pin_table: Vec<Vec<String>> = Vec::new();
let mut interrupt_table: Vec<Vec<String>> = Vec::new();
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
let dma_base = chip
.peripherals
.get(&"DMA".to_string())
.unwrap_or_else(|| chip.peripherals.get(&"DMA1".to_string()).unwrap())
.address;
let dma_stride = 0x400;
let gpio_base = chip.peripherals.get(&"GPIOA".to_string()).unwrap().address;
let gpio_stride = 0x400;
for (name, p) in &chip.peripherals {
let mut ir_peri = ir::Peripheral {
name: name.clone(),
array: None,
base_address: p.address,
block: None,
description: None,
interrupts: HashMap::new(),
};
if let Some(block) = &p.block {
let bi = BlockInfo::parse(block);
for pin in &p.pins {
let mut row = Vec::new();
row.push(name.clone());
row.push(bi.module.clone());
row.push(bi.block.clone());
row.push(pin.pin.clone());
row.push(pin.signal.clone());
if let Some(ref af) = pin.af {
row.push(af.clone());
}
peripheral_pins_table.push(row);
}
let mut peripheral_row = Vec::new();
peripheral_row.push(bi.module.clone());
peripheral_row.push(name.clone());
peripherals_table.push(peripheral_row);
if let Some(old_version) =
peripheral_versions.insert(bi.module.clone(), bi.version.clone())
{
if old_version != bi.version {
panic!(
"Peripheral {} has multiple versions: {} and {}",
bi.module, old_version, bi.version
);
}
}
ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
match bi.module.as_str() {
"gpio" => {
let port_letter = name.chars().skip(4).next().unwrap();
let port_num = port_letter as u32 - 'A' as u32;
assert_eq!(p.address, gpio_base + gpio_stride * port_num);
for pin_num in 0..16 {
let pin_name = format!("P{}{}", port_letter, pin_num);
pin_table.push(vec![
pin_name.clone(),
name.clone(),
port_num.to_string(),
pin_num.to_string(),
format!("EXTI{}", pin_num),
]);
}
}
"dma" => {
let dma_num = if name == "DMA" {
0
} else {
let dma_letter = name.chars().skip(3).next().unwrap();
dma_letter as u32 - '1' as u32
};
assert_eq!(p.address, dma_base + dma_stride * dma_num);
}
_ => {}
}
if let Some(clock) = &p.clock {
if let Some(rcc) = &rcc {
// Workaround for clock registers being split on some chip families. Assume fields are
// named after peripheral and look for first field matching and use that register.
let en = find_reg_for_field(&rcc, clock, &format!("{}EN", name));
let rst = find_reg_for_field(&rcc, clock, &format!("{}RST", name));
match (en, rst) {
(Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
peripheral_rcc_table.push(vec![
name.clone(),
enable_reg.to_ascii_lowercase(),
reset_reg.to_ascii_lowercase(),
format!("set_{}", enable_field.to_ascii_lowercase()),
format!("set_{}", reset_field.to_ascii_lowercase()),
]);
}
(None, Some(_)) => {
println!("Unable to find enable register for {}", name)
}
(Some(_), None) => {
println!("Unable to find reset register for {}", name)
}
(None, None) => {
println!("Unable to find enable and reset register for {}", name)
}
}
}
}
}
dev.peripherals.push(ir_peri);
}
for (name, &num) in &chip.interrupts {
dev.interrupts.push(ir::Interrupt {
name: name.clone(),
description: None,
value: num,
});
interrupt_table.push(vec![name.to_ascii_uppercase()]);
}
ir.devices.insert("".to_string(), dev);
let mut extra = format!(
"pub fn GPIO(n: usize) -> gpio::Gpio {{
gpio::Gpio(({} + {}*n) as _)
}}
pub fn DMA(n: usize) -> dma::Dma {{
dma::Dma(({} + {}*n) as _)
}}",
gpio_base, gpio_stride, dma_base, dma_stride,
println!(
"cargo:rustc-link-search={}/src/chips/{}",
out_dir.display(),
chip_name.to_ascii_lowercase()
);
let peripheral_version_table = peripheral_versions
.iter()
.map(|(kind, version)| vec![kind.clone(), version.clone()])
.collect();
make_table(&mut extra, "pins", &pin_table);
make_table(&mut extra, "interrupts", &interrupt_table);
make_table(&mut extra, "peripherals", &peripherals_table);
make_table(&mut extra, "peripheral_versions", &peripheral_version_table);
make_table(&mut extra, "peripheral_pins", &peripheral_pins_table);
make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table);
for (module, version) in peripheral_versions {
println!("loading {} {}", module, version);
let regs_path = Path::new(&dir)
.join("registers")
.join(&format!("{}_{}.yaml", module, version));
let mut peri: ir::IR = serde_yaml::from_reader(File::open(regs_path).unwrap()).unwrap();
transform::expand_extends::ExpandExtends {}
.run(&mut peri)
.unwrap();
let prefix = module;
transform::map_names(&mut peri, |s, k| match k {
transform::NameKind::Block => format!("{}::{}", prefix, s),
transform::NameKind::Fieldset => format!("{}::regs::{}", prefix, s),
transform::NameKind::Enum => format!("{}::vals::{}", prefix, s),
_ => s.to_string(),
})
.unwrap();
ir.merge(peri);
}
// Cleanups!
transform::sort::Sort {}.run(&mut ir).unwrap();
transform::Sanitize {}.run(&mut ir).unwrap();
let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
let items = generate::render(&ir).unwrap();
let mut file = File::create(out.join("pac.rs")).unwrap();
let data = items.to_string().replace("] ", "]\n");
// Remove inner attributes like #![no_std]
let re = Regex::new("# *! *\\[.*\\]").unwrap();
let data = re.replace_all(&data, "");
file.write_all(data.as_bytes()).unwrap();
file.write_all(extra.as_bytes()).unwrap();
let mut device_x = String::new();
for (name, _) in &chip.interrupts {
write!(
&mut device_x,
"PROVIDE({} = DefaultHandler);\n",
name.to_ascii_uppercase()
)
.unwrap();
}
File::create(out.join("device.x"))
.unwrap()
.write_all(device_x.as_bytes())
.unwrap();
println!("cargo:rustc-link-search={}", out.display());
println!("cargo:rerun-if-changed=build.rs");
}

3
stm32-metapac/gen/.vscode/settings.json vendored Normal file
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@ -0,0 +1,3 @@
{
"editor.formatOnSave": true
}

12
stm32-metapac/gen/Cargo.toml Normal file
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@ -0,0 +1,12 @@
[package]
name = "stm32-metapac-gen"
version = "0.1.0"
edition = "2018"
[dependencies]
regex = "1.4.6"
chiptool = { git = "https://github.com/embassy-rs/chiptool", rev = "b905099423280cdc39a96bc51f0b669ddb443797" }
serde = { version = "1.0.123", features = [ "derive" ]}
serde_yaml = "0.8.15"
syn = { version = "1.0", features = ["full","extra-traits"] }

16
stm32-metapac/gen/src/assets/build.rs Normal file
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@ -0,0 +1,16 @@
use std::env;
fn main() {
let _chip_name = env::vars_os()
.map(|(a, _)| a.to_string_lossy().to_string())
.find(|x| x.starts_with("CARGO_FEATURE_STM32"))
.expect("No stm32xx Cargo feature enabled")
.strip_prefix("CARGO_FEATURE_")
.unwrap()
.to_ascii_lowercase();
#[cfg(feature = "rt")]
println!("cargo:rustc-link-search=src/chips/{}", _chip_name);
println!("cargo:rerun-if-changed=build.rs");
}

6
stm32-metapac/gen/src/assets/lib_inner.rs Normal file
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@ -0,0 +1,6 @@
// GEN PATHS HERE
mod inner;
pub mod common;
pub use inner::*;

477
stm32-metapac/gen/src/lib.rs Normal file
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@ -0,0 +1,477 @@
use regex::Regex;
use serde::Deserialize;
use std::collections::{HashMap, HashSet};
use std::env;
use std::fmt::Write as _;
use std::fs;
use std::fs::File;
use std::io::Write;
use std::path::Path;
use std::path::PathBuf;
use chiptool::{generate, ir, transform};
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Chip {
pub name: String,
pub family: String,
pub line: String,
pub core: String,
pub flash: u32,
pub ram: u32,
pub gpio_af: String,
pub packages: Vec<Package>,
pub peripherals: HashMap<String, Peripheral>,
pub interrupts: HashMap<String, u32>,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Package {
pub name: String,
pub package: String,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Peripheral {
pub address: u32,
#[serde(default)]
pub kind: Option<String>,
#[serde(default)]
pub block: Option<String>,
#[serde(default)]
pub clock: Option<String>,
#[serde(default)]
pub pins: Vec<Pin>,
}
#[derive(Debug, Eq, PartialEq, Clone, Deserialize)]
pub struct Pin {
pub pin: String,
pub signal: String,
pub af: Option<String>,
}
struct BlockInfo {
/// usart_v1/USART -> usart
module: String,
/// usart_v1/USART -> v1
version: String,
/// usart_v1/USART -> USART
block: String,
}
impl BlockInfo {
fn parse(s: &str) -> Self {
let mut s = s.split("/");
let module = s.next().unwrap();
let block = s.next().unwrap();
assert!(s.next().is_none());
let mut s = module.split("_");
let module = s.next().unwrap();
let version = s.next().unwrap();
assert!(s.next().is_none());
Self {
module: module.to_string(),
version: version.to_string(),
block: block.to_string(),
}
}
}
fn find_reg_for_field<'c>(
rcc: &'c ir::IR,
reg_prefix: &str,
field_name: &str,
) -> Option<(&'c str, &'c str)> {
rcc.fieldsets.iter().find_map(|(name, fieldset)| {
if name.starts_with(reg_prefix) {
fieldset
.fields
.iter()
.find_map(|field| {
if field_name == field.name {
return Some(field.name.as_str());
} else {
None
}
})
.map(|n| (name.as_str(), n))
} else {
None
}
})
}
fn make_table(out: &mut String, name: &str, data: &Vec<Vec<String>>) {
write!(
out,
"#[macro_export]
macro_rules! {} {{
($($pat:tt => $code:tt;)*) => {{
macro_rules! __{}_inner {{
$(($pat) => $code;)*
($_:tt) => {{}}
}}
",
name, name
)
.unwrap();
for row in data {
write!(out, " __{}_inner!(({}));\n", name, row.join(",")).unwrap();
}
write!(
out,
" }};
}}"
)
.unwrap();
}
pub struct Options {
pub chips: Vec<String>,
pub out_dir: PathBuf,
pub data_dir: PathBuf,
}
pub fn gen(options: Options) {
let generate_opts = generate::Options {
common_path: syn::parse_str("crate::common").unwrap(),
};
let out_dir = options.out_dir;
let data_dir = options.data_dir;
fs::create_dir_all(out_dir.join("src/peripherals")).unwrap();
fs::create_dir_all(out_dir.join("src/chips")).unwrap();
println!("cwd: {:?}", env::current_dir());
let mut all_peripheral_versions: HashSet<(String, String)> = HashSet::new();
for chip_name in &options.chips {
let chip_path = data_dir.join("chips").join(&format!("{}.yaml", chip_name));
println!("chip_path: {:?}", chip_path);
let chip = fs::read(chip_path).unwrap();
let chip: Chip = serde_yaml::from_slice(&chip).unwrap();
let mut ir = ir::IR::new();
let mut dev = ir::Device {
interrupts: Vec::new(),
peripherals: Vec::new(),
};
// Load RCC register for chip
let rcc = chip.peripherals.iter().find_map(|(name, p)| {
if name == "RCC" {
p.block.as_ref().map(|block| {
let bi = BlockInfo::parse(block);
let rcc_reg_path = data_dir
.join("registers")
.join(&format!("{}_{}.yaml", bi.module, bi.version));
serde_yaml::from_reader(File::open(rcc_reg_path).unwrap()).unwrap()
})
} else {
None
}
});
let mut peripheral_versions: HashMap<String, String> = HashMap::new();
let mut pin_table: Vec<Vec<String>> = Vec::new();
let mut interrupt_table: Vec<Vec<String>> = Vec::new();
let mut peripherals_table: Vec<Vec<String>> = Vec::new();
let mut peripheral_pins_table: Vec<Vec<String>> = Vec::new();
let mut peripheral_rcc_table: Vec<Vec<String>> = Vec::new();
let dma_base = chip
.peripherals
.get(&"DMA".to_string())
.unwrap_or_else(|| chip.peripherals.get(&"DMA1".to_string()).unwrap())
.address;
let dma_stride = 0x400;
let gpio_base = chip.peripherals.get(&"GPIOA".to_string()).unwrap().address;
let gpio_stride = 0x400;
for (name, p) in &chip.peripherals {
let mut ir_peri = ir::Peripheral {
name: name.clone(),
array: None,
base_address: p.address,
block: None,
description: None,
interrupts: HashMap::new(),
};
if let Some(block) = &p.block {
let bi = BlockInfo::parse(block);
for pin in &p.pins {
let mut row = Vec::new();
row.push(name.clone());
row.push(bi.module.clone());
row.push(bi.block.clone());
row.push(pin.pin.clone());
row.push(pin.signal.clone());
if let Some(ref af) = pin.af {
row.push(af.clone());
}
peripheral_pins_table.push(row);
}
let mut peripheral_row = Vec::new();
peripheral_row.push(bi.module.clone());
peripheral_row.push(name.clone());
peripherals_table.push(peripheral_row);
if let Some(old_version) =
peripheral_versions.insert(bi.module.clone(), bi.version.clone())
{
if old_version != bi.version {
panic!(
"Peripheral {} has multiple versions: {} and {}",
bi.module, old_version, bi.version
);
}
}
ir_peri.block = Some(format!("{}::{}", bi.module, bi.block));
match bi.module.as_str() {
"gpio" => {
let port_letter = name.chars().skip(4).next().unwrap();
let port_num = port_letter as u32 - 'A' as u32;
assert_eq!(p.address, gpio_base + gpio_stride * port_num);
for pin_num in 0..16 {
let pin_name = format!("P{}{}", port_letter, pin_num);
pin_table.push(vec![
pin_name.clone(),
name.clone(),
port_num.to_string(),
pin_num.to_string(),
format!("EXTI{}", pin_num),
]);
}
}
"dma" => {
let dma_num = if name == "DMA" {
0
} else {
let dma_letter = name.chars().skip(3).next().unwrap();
dma_letter as u32 - '1' as u32
};
assert_eq!(p.address, dma_base + dma_stride * dma_num);
}
_ => {}
}
if let Some(clock) = &p.clock {
if let Some(rcc) = &rcc {
// Workaround for clock registers being split on some chip families. Assume fields are
// named after peripheral and look for first field matching and use that register.
let en = find_reg_for_field(&rcc, clock, &format!("{}EN", name));
let rst = find_reg_for_field(&rcc, clock, &format!("{}RST", name));
match (en, rst) {
(Some((enable_reg, enable_field)), Some((reset_reg, reset_field))) => {
peripheral_rcc_table.push(vec![
name.clone(),
enable_reg.to_ascii_lowercase(),
reset_reg.to_ascii_lowercase(),
format!("set_{}", enable_field.to_ascii_lowercase()),
format!("set_{}", reset_field.to_ascii_lowercase()),
]);
}
(None, Some(_)) => {
println!("Unable to find enable register for {}", name)
}
(Some(_), None) => {
println!("Unable to find reset register for {}", name)
}
(None, None) => {
println!("Unable to find enable and reset register for {}", name)
}
}
}
}
}
dev.peripherals.push(ir_peri);
}
for (name, &num) in &chip.interrupts {
dev.interrupts.push(ir::Interrupt {
name: name.clone(),
description: None,
value: num,
});
interrupt_table.push(vec![name.to_ascii_uppercase()]);
}
ir.devices.insert("".to_string(), dev);
let mut extra = format!(
"pub fn GPIO(n: usize) -> gpio::Gpio {{
gpio::Gpio(({} + {}*n) as _)
}}
pub fn DMA(n: usize) -> dma::Dma {{
dma::Dma(({} + {}*n) as _)
}}",
gpio_base, gpio_stride, dma_base, dma_stride,
);
let peripheral_version_table = peripheral_versions
.iter()
.map(|(kind, version)| vec![kind.clone(), version.clone()])
.collect();
make_table(&mut extra, "pins", &pin_table);
make_table(&mut extra, "interrupts", &interrupt_table);
make_table(&mut extra, "peripherals", &peripherals_table);
make_table(&mut extra, "peripheral_versions", &peripheral_version_table);
make_table(&mut extra, "peripheral_pins", &peripheral_pins_table);
make_table(&mut extra, "peripheral_rcc", &peripheral_rcc_table);
for (module, version) in peripheral_versions {
all_peripheral_versions.insert((module.clone(), version.clone()));
write!(
&mut extra,
"#[path=\"../../peripherals/{}_{}.rs\"] pub mod {};\n",
module, version, module
)
.unwrap();
}
// Cleanups!
transform::sort::Sort {}.run(&mut ir).unwrap();
transform::Sanitize {}.run(&mut ir).unwrap();
let chip_dir = out_dir
.join("src/chips")
.join(chip_name.to_ascii_lowercase());
fs::create_dir_all(&chip_dir).unwrap();
let items = generate::render(&ir, &generate_opts).unwrap();
let mut file = File::create(chip_dir.join("pac.rs")).unwrap();
let data = items.to_string().replace("] ", "]\n");
// Remove inner attributes like #![no_std]
let re = Regex::new("# *! *\\[.*\\]").unwrap();
let data = re.replace_all(&data, "");
file.write_all(data.as_bytes()).unwrap();
file.write_all(extra.as_bytes()).unwrap();
let mut device_x = String::new();
for (name, _) in &chip.interrupts {
write!(
&mut device_x,
"PROVIDE({} = DefaultHandler);\n",
name.to_ascii_uppercase()
)
.unwrap();
}
File::create(chip_dir.join("device.x"))
.unwrap()
.write_all(device_x.as_bytes())
.unwrap();
}
for (module, version) in all_peripheral_versions {
println!("loading {} {}", module, version);
let regs_path = Path::new(&data_dir)
.join("registers")
.join(&format!("{}_{}.yaml", module, version));
let mut ir: ir::IR = serde_yaml::from_reader(File::open(regs_path).unwrap()).unwrap();
transform::expand_extends::ExpandExtends {}
.run(&mut ir)
.unwrap();
transform::map_names(&mut ir, |s, k| match k {
transform::NameKind::Block => format!("{}", s),
transform::NameKind::Fieldset => format!("regs::{}", s),
transform::NameKind::Enum => format!("vals::{}", s),
_ => s.to_string(),
})
.unwrap();
transform::sort::Sort {}.run(&mut ir).unwrap();
transform::Sanitize {}.run(&mut ir).unwrap();
let items = generate::render(&ir, &generate_opts).unwrap();
let mut file = File::create(
out_dir
.join("src/peripherals")
.join(format!("{}_{}.rs", module, version)),
)
.unwrap();
let data = items.to_string().replace("] ", "]\n");
// Remove inner attributes like #![no_std]
let re = Regex::new("# *! *\\[.*\\]").unwrap();
let data = re.replace_all(&data, "");
file.write_all(data.as_bytes()).unwrap();
}
// Generate src/lib_inner.rs
const PATHS_MARKER: &[u8] = b"// GEN PATHS HERE";
let librs = include_bytes!("assets/lib_inner.rs");
let i = bytes_find(librs, PATHS_MARKER).unwrap();
let mut paths = String::new();
for chip_name in &options.chips {
let x = chip_name.to_ascii_lowercase();
write!(
&mut paths,
"#[cfg_attr(feature=\"{}\", path = \"chips/{}/pac.rs\")]",
x, x
)
.unwrap();
}
let mut contents: Vec<u8> = Vec::new();
contents.extend(&librs[..i]);
contents.extend(paths.as_bytes());
contents.extend(&librs[i + PATHS_MARKER.len()..]);
fs::write(out_dir.join("src").join("lib_inner.rs"), &contents).unwrap();
// Generate src/lib.rs
const CUT_MARKER: &[u8] = b"// GEN CUT HERE";
let librs = include_bytes!("../../src/lib.rs");
let i = bytes_find(librs, CUT_MARKER).unwrap();
let mut contents: Vec<u8> = Vec::new();
contents.extend(&librs[..i]);
contents.extend(b"include!(\"lib_inner.rs\");\n");
fs::write(out_dir.join("src").join("lib.rs"), contents).unwrap();
// Generate src/common.rs
fs::write(
out_dir.join("src").join("common.rs"),
generate::COMMON_MODULE,
)
.unwrap();
// Generate Cargo.toml
const BUILDDEP_BEGIN: &[u8] = b"# BEGIN BUILD DEPENDENCIES";
const BUILDDEP_END: &[u8] = b"# END BUILD DEPENDENCIES";
let mut contents = include_bytes!("../../Cargo.toml").to_vec();
let begin = bytes_find(&contents, BUILDDEP_BEGIN).unwrap();
let end = bytes_find(&contents, BUILDDEP_END).unwrap() + BUILDDEP_END.len();
contents.drain(begin..end);
fs::write(out_dir.join("Cargo.toml"), contents).unwrap();
// Generate build.rs
fs::write(out_dir.join("build.rs"), include_bytes!("assets/build.rs")).unwrap();
}
fn bytes_find(haystack: &[u8], needle: &[u8]) -> Option<usize> {
haystack
.windows(needle.len())
.position(|window| window == needle)
}

21
stm32-metapac/gen/src/main.rs Normal file
View File

@ -0,0 +1,21 @@
use std::path::PathBuf;
use stm32_metapac_gen::*;
fn main() {
let out_dir = PathBuf::from("out");
let data_dir = PathBuf::from("../../stm32-data/data");
let chips = std::fs::read_dir(data_dir.join("chips"))
.unwrap()
.filter_map(|res| res.unwrap().file_name().to_str().map(|s| s.to_string()))
.filter(|s| s.ends_with(".yaml"))
.filter(|s| !s.starts_with("STM32L1")) // cursed gpio stride
.map(|s| s.strip_suffix(".yaml").unwrap().to_string())
.collect();
gen(Options {
out_dir,
data_dir,
chips,
})
}

3
stm32-metapac/src/lib.rs
View File

@ -3,4 +3,5 @@
#![allow(unused)]
#![allow(non_camel_case_types)]
include!(concat!(env!("OUT_DIR"), "/pac.rs"));
// GEN CUT HERE
include!(concat!(env!("OUT_DIR"), "/src/lib_inner.rs"));