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stm32: fix uart parity, add comment why it is so

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This commit is contained in:
Andres Vahter 2023-10-24 15:57:03 +03:00
parent 25c2a9baaa
commit bda99e59ec
1 changed files with 11 additions and 8 deletions
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19
embassy-stm32/src/usart/mod.rs
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@ -974,6 +974,12 @@ fn configure(
#[cfg(any(usart_v3, usart_v4))]
w.set_swap(config.swap_rx_tx);
});
#[cfg(not(usart_v1))]
r.cr3().modify(|w| {
w.set_onebit(config.assume_noise_free);
});
r.cr1().write(|w| {
// enable uart
w.set_ue(true);
@ -982,9 +988,11 @@ fn configure(
// enable receiver
w.set_re(enable_rx);
// configure word size
w.set_m0(match config.data_bits {
DataBits::DataBits8 => vals::M0::BIT8,
DataBits::DataBits9 => vals::M0::BIT9,
// if using odd or even parity it must be configured to 9bits
w.set_m0(if config.parity != Parity::ParityNone {
vals::M0::BIT9
} else {
vals::M0::BIT8
});
// configure parity
w.set_pce(config.parity != Parity::ParityNone);
@ -999,11 +1007,6 @@ fn configure(
w.set_fifoen(true);
});
#[cfg(not(usart_v1))]
r.cr3().modify(|w| {
w.set_onebit(config.assume_noise_free);
});
Ok(())
}