rp/uart: make dma multicore-safe
running rx and tx on different cores could lead to hangs if the dmacr register modifys run concurrently. this is bad.
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@ -206,7 +206,7 @@ impl<'d, T: Instance> UartTx<'d, T, Async> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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pub async fn write(&mut self, buffer: &[u8]) -> Result<(), Error> {
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let ch = self.tx_dma.as_mut().unwrap();
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let ch = self.tx_dma.as_mut().unwrap();
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let transfer = unsafe {
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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T::regs().uartdmacr().write_set(|reg| {
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reg.set_txdmae(true);
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reg.set_txdmae(true);
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});
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});
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// If we don't assign future to a variable, the data register pointer
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// If we don't assign future to a variable, the data register pointer
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@ -296,7 +296,7 @@ impl<'d, T: Instance> UartRx<'d, T, Async> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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pub async fn read(&mut self, buffer: &mut [u8]) -> Result<(), Error> {
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let ch = self.rx_dma.as_mut().unwrap();
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let ch = self.rx_dma.as_mut().unwrap();
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let transfer = unsafe {
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let transfer = unsafe {
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T::regs().uartdmacr().modify(|reg| {
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T::regs().uartdmacr().write_set(|reg| {
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reg.set_rxdmae(true);
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reg.set_rxdmae(true);
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});
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});
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// If we don't assign future to a variable, the data register pointer
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// If we don't assign future to a variable, the data register pointer
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