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Update ringbuffer to only work on half, add prime

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This commit is contained in:
Tyler Gilbert 2023-12-04 22:07:03 -06:00
parent 4a94a5259f
commit c27d63e754
1 changed files with 15 additions and 1 deletions
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16
embassy-stm32/src/dma/ringbuffer.rs
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@ -260,7 +260,21 @@ impl<'a, W: Word> WritableDmaRingBuffer<'a, W> {
/// The current position of the ringbuffer /// The current position of the ringbuffer
fn pos(&self, dma: &mut impl DmaCtrl) -> usize { fn pos(&self, dma: &mut impl DmaCtrl) -> usize {
self.cap() - dma.get_remaining_transfers() let result = self.cap() - dma.get_remaining_transfers();
if result >= self.cap() / 2 {
self.cap() / 2
} else {
0
}
}
pub fn prime(&mut self, dma: &mut impl DmaCtrl, buffer: &[W]) -> Result<(usize, usize), OverrunError> {
if self.end != 0 {
return Err(OverrunError);
}
let written = self.copy_from(buffer, 0..self.cap());
self.end = written % self.cap();
Ok((written, self.cap() - written))
} }
/// Write an exact number of elements to the ringbuffer. /// Write an exact number of elements to the ringbuffer.