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net-w5500: add Address type.

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This commit is contained in:
Dario Nieuwenhuis
2023-08-15 17:11:24 +02:00
parent 46f671ae42
commit c367b84ee5
3 changed files with 44 additions and 53 deletions
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41
embassy-net-w5500/src/device.rs
View File

@@ -1,12 +1,12 @@
use embedded_hal_async::spi::SpiDevice;
use crate::socket;
use crate::spi::SpiInterface;
use crate::spi::{Address, SpiInterface};
pub const MODE: u16 = 0x00;
pub const MAC: u16 = 0x09;
pub const SOCKET_INTR: u16 = 0x18;
pub const PHY_CFG: u16 = 0x2E;
pub const MODE: Address = (RegisterBlock::Common, 0x00);
pub const MAC: Address = (RegisterBlock::Common, 0x09);
pub const SOCKET_INTR: Address = (RegisterBlock::Common, 0x18);
pub const PHY_CFG: Address = (RegisterBlock::Common, 0x2E);
#[repr(u8)]
pub enum RegisterBlock {
@@ -28,30 +28,24 @@ impl<SPI: SpiDevice> W5500<SPI> {
pub async fn new(spi: SPI, mac_addr: [u8; 6]) -> Result<W5500<SPI>, SPI::Error> {
let mut bus = SpiInterface(spi);
// Reset device
bus.write_frame(RegisterBlock::Common, MODE, &[0x80]).await?;
bus.write_frame(MODE, &[0x80]).await?;
// Enable interrupt pin
bus.write_frame(RegisterBlock::Common, SOCKET_INTR, &[0x01]).await?;
bus.write_frame(SOCKET_INTR, &[0x01]).await?;
// Enable receive interrupt
bus.write_frame(
RegisterBlock::Socket0,
socket::SOCKET_INTR_MASK,
&[socket::Interrupt::Receive as u8],
)
.await?;
bus.write_frame(socket::SOCKET_INTR_MASK, &[socket::Interrupt::Receive as u8])
.await?;
// Set MAC address
bus.write_frame(RegisterBlock::Common, MAC, &mac_addr).await?;
bus.write_frame(MAC, &mac_addr).await?;
// Set the raw socket RX/TX buffer sizes to 16KB
bus.write_frame(RegisterBlock::Socket0, socket::TXBUF_SIZE, &[16])
.await?;
bus.write_frame(RegisterBlock::Socket0, socket::RXBUF_SIZE, &[16])
.await?;
bus.write_frame(socket::TXBUF_SIZE, &[16]).await?;
bus.write_frame(socket::RXBUF_SIZE, &[16]).await?;
// MACRAW mode with MAC filtering.
let mode: u8 = (1 << 2) | (1 << 7);
bus.write_frame(RegisterBlock::Socket0, socket::MODE, &[mode]).await?;
bus.write_frame(socket::MODE, &[mode]).await?;
socket::command(&mut bus, socket::Command::Open).await?;
Ok(Self { bus })
@@ -59,7 +53,7 @@ impl<SPI: SpiDevice> W5500<SPI> {
/// Read bytes from the RX buffer. Returns the number of bytes read.
async fn read_bytes(&mut self, read_ptr: &mut u16, buffer: &mut [u8]) -> Result<(), SPI::Error> {
self.bus.read_frame(RegisterBlock::RxBuf, *read_ptr, buffer).await?;
self.bus.read_frame((RegisterBlock::RxBuf, *read_ptr), buffer).await?;
*read_ptr = (*read_ptr).wrapping_add(buffer.len() as u16);
Ok(())
@@ -98,7 +92,7 @@ impl<SPI: SpiDevice> W5500<SPI> {
pub async fn write_frame(&mut self, frame: &[u8]) -> Result<usize, SPI::Error> {
while socket::get_tx_free_size(&mut self.bus).await? < frame.len() as u16 {}
let write_ptr = socket::get_tx_write_ptr(&mut self.bus).await?;
self.bus.write_frame(RegisterBlock::TxBuf, write_ptr, frame).await?;
self.bus.write_frame((RegisterBlock::TxBuf, write_ptr), frame).await?;
socket::set_tx_write_ptr(&mut self.bus, write_ptr.wrapping_add(frame.len() as u16)).await?;
socket::command(&mut self.bus, socket::Command::Send).await?;
Ok(frame.len())
@@ -106,10 +100,7 @@ impl<SPI: SpiDevice> W5500<SPI> {
pub async fn is_link_up(&mut self) -> bool {
let mut link = [0];
self.bus
.read_frame(RegisterBlock::Common, PHY_CFG, &mut link)
.await
.ok();
self.bus.read_frame(PHY_CFG, &mut link).await.ok();
link[0] & 1 == 1
}
}

42
embassy-net-w5500/src/socket.rs
View File

@@ -1,17 +1,18 @@
use embedded_hal_async::spi::SpiDevice;
use crate::device::RegisterBlock;
use crate::spi::SpiInterface;
use crate::spi::{Address, SpiInterface};
pub const MODE: u16 = 0x00;
pub const COMMAND: u16 = 0x01;
pub const RXBUF_SIZE: u16 = 0x1E;
pub const TXBUF_SIZE: u16 = 0x1F;
pub const TX_FREE_SIZE: u16 = 0x20;
pub const TX_DATA_WRITE_PTR: u16 = 0x24;
pub const RECVD_SIZE: u16 = 0x26;
pub const RX_DATA_READ_PTR: u16 = 0x28;
pub const SOCKET_INTR_MASK: u16 = 0x2C;
pub const MODE: Address = (RegisterBlock::Socket0, 0x00);
pub const COMMAND: Address = (RegisterBlock::Socket0, 0x01);
pub const RXBUF_SIZE: Address = (RegisterBlock::Socket0, 0x1E);
pub const TXBUF_SIZE: Address = (RegisterBlock::Socket0, 0x1F);
pub const TX_FREE_SIZE: Address = (RegisterBlock::Socket0, 0x20);
pub const TX_DATA_WRITE_PTR: Address = (RegisterBlock::Socket0, 0x24);
pub const RECVD_SIZE: Address = (RegisterBlock::Socket0, 0x26);
pub const RX_DATA_READ_PTR: Address = (RegisterBlock::Socket0, 0x28);
pub const SOCKET_INTR_MASK: Address = (RegisterBlock::Socket0, 0x2C);
pub const INTR: Address = (RegisterBlock::Socket0, 0x02);
#[repr(u8)]
pub enum Command {
@@ -20,7 +21,6 @@ pub enum Command {
Receive = 0x40,
}
pub const INTR: u16 = 0x02;
#[repr(u8)]
pub enum Interrupt {
Receive = 0b00100_u8,
@@ -28,45 +28,43 @@ pub enum Interrupt {
pub async fn reset_interrupt<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, code: Interrupt) -> Result<(), SPI::Error> {
let data = [code as u8];
bus.write_frame(RegisterBlock::Socket0, INTR, &data).await
bus.write_frame(INTR, &data).await
}
pub async fn get_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
let mut data = [0u8; 2];
bus.read_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &mut data)
.await?;
bus.read_frame(TX_DATA_WRITE_PTR, &mut data).await?;
Ok(u16::from_be_bytes(data))
}
pub async fn set_tx_write_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
let data = ptr.to_be_bytes();
bus.write_frame(RegisterBlock::Socket0, TX_DATA_WRITE_PTR, &data).await
bus.write_frame(TX_DATA_WRITE_PTR, &data).await
}
pub async fn get_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
let mut data = [0u8; 2];
bus.read_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &mut data)
.await?;
bus.read_frame(RX_DATA_READ_PTR, &mut data).await?;
Ok(u16::from_be_bytes(data))
}
pub async fn set_rx_read_ptr<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, ptr: u16) -> Result<(), SPI::Error> {
let data = ptr.to_be_bytes();
bus.write_frame(RegisterBlock::Socket0, RX_DATA_READ_PTR, &data).await
bus.write_frame(RX_DATA_READ_PTR, &data).await
}
pub async fn command<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>, command: Command) -> Result<(), SPI::Error> {
let data = [command as u8];
bus.write_frame(RegisterBlock::Socket0, COMMAND, &data).await
bus.write_frame(COMMAND, &data).await
}
pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
loop {
// Wait until two sequential reads are equal
let mut res0 = [0u8; 2];
bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res0).await?;
bus.read_frame(RECVD_SIZE, &mut res0).await?;
let mut res1 = [0u8; 2];
bus.read_frame(RegisterBlock::Socket0, RECVD_SIZE, &mut res1).await?;
bus.read_frame(RECVD_SIZE, &mut res1).await?;
if res0 == res1 {
break Ok(u16::from_be_bytes(res0));
}
@@ -75,6 +73,6 @@ pub async fn get_rx_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<
pub async fn get_tx_free_size<SPI: SpiDevice>(bus: &mut SpiInterface<SPI>) -> Result<u16, SPI::Error> {
let mut data = [0; 2];
bus.read_frame(RegisterBlock::Socket0, TX_FREE_SIZE, &mut data).await?;
bus.read_frame(TX_FREE_SIZE, &mut data).await?;
Ok(u16::from_be_bytes(data))
}

14
embassy-net-w5500/src/spi.rs
View File

@@ -2,14 +2,16 @@ use embedded_hal_async::spi::{Operation, SpiDevice};
use crate::device::RegisterBlock;
pub type Address = (RegisterBlock, u16);
#[derive(Debug)]
#[cfg_attr(feature = "defmt", derive(defmt::Format))]
pub struct SpiInterface<SPI>(pub SPI);
impl<SPI: SpiDevice> SpiInterface<SPI> {
pub async fn read_frame(&mut self, block: RegisterBlock, address: u16, data: &mut [u8]) -> Result<(), SPI::Error> {
let address_phase = address.to_be_bytes();
let control_phase = [(block as u8) << 3];
pub async fn read_frame(&mut self, address: Address, data: &mut [u8]) -> Result<(), SPI::Error> {
let address_phase = address.1.to_be_bytes();
let control_phase = [(address.0 as u8) << 3];
let operations = &mut [
Operation::Write(&address_phase),
Operation::Write(&control_phase),
@@ -18,9 +20,9 @@ impl<SPI: SpiDevice> SpiInterface<SPI> {
self.0.transaction(operations).await
}
pub async fn write_frame(&mut self, block: RegisterBlock, address: u16, data: &[u8]) -> Result<(), SPI::Error> {
let address_phase = address.to_be_bytes();
let control_phase = [(block as u8) << 3 | 0b0000_0100];
pub async fn write_frame(&mut self, address: Address, data: &[u8]) -> Result<(), SPI::Error> {
let address_phase = address.1.to_be_bytes();
let control_phase = [(address.0 as u8) << 3 | 0b0000_0100];
let data_phase = data;
let operations = &mut [
Operation::Write(&address_phase[..]),