Merge #1046
1046: embassy-stm32: Fix bug when Uart::read future is dropped and DMA request was not stopped r=lulf a=guillaume-michel fixes #1045 regression was introduced with PR #1031 Co-authored-by: Guillaume MICHEL <guillaume@squaremind.io>
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@@ -6,6 +6,8 @@ use core::task::Poll;
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use atomic_polyfill::{compiler_fence, Ordering};
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use embassy_cortex_m::interrupt::InterruptExt;
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use embassy_futures::select::{select, Either};
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use embassy_hal_common::drop::OnDrop;
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use embassy_hal_common::{into_ref, PeripheralRef};
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use crate::dma::NoDma;
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@@ -85,6 +87,13 @@ pub enum Error {
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BufferTooLong,
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}
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enum ReadCompletionEvent {
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// DMA Read transfer completed first
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DmaCompleted,
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// Idle line detected first
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Idle,
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}
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pub struct Uart<'d, T: BasicInstance, TxDma = NoDma, RxDma = NoDma> {
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tx: UartTx<'d, T, TxDma>,
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rx: UartRx<'d, T, RxDma>,
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@@ -385,30 +394,50 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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self.inner_read(buffer, true).await
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}
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async fn inner_read(&mut self, buffer: &mut [u8], enable_idle_line_detection: bool) -> Result<usize, Error>
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async fn inner_read_run(
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&mut self,
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buffer: &mut [u8],
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enable_idle_line_detection: bool,
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) -> Result<ReadCompletionEvent, Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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if buffer.is_empty() {
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return Ok(0);
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} else if buffer.len() > 0xFFFF {
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return Err(Error::BufferTooLong);
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}
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let r = T::regs();
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let buffer_len = buffer.len();
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// make sure USART state is restored to neutral state when this future is dropped
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let _drop = OnDrop::new(move || {
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// defmt::trace!("Clear all USART interrupts and DMA Read Request");
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// clear all interrupts and DMA Rx Request
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// SAFETY: only clears Rx related flags
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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}
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});
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let ch = &mut self.rx_dma;
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let request = ch.request();
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// Start USART DMA
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// will not do anything yet because DMAR is not yet set
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// future which will complete when DMA Read request completes
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let transfer = crate::dma::read(ch, request, rdr(T::regs()), buffer);
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// SAFETY: The only way we might have a problem is using split rx and tx
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// here we only modify or read Rx related flags, interrupts and DMA channel
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unsafe {
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// Start USART DMA
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// will not do anything yet because DMAR is not yet set
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ch.start_read(request, rdr(r), buffer, Default::default());
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// clear ORE flag just before enabling DMA Rx Request: can be mandatory for the second transfer
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if !self.detect_previous_overrun {
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let sr = sr(r).read();
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@@ -443,9 +472,7 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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// something went wrong
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// because the only way to get this flag cleared is to have an interrupt
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// abort DMA transfer
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ch.request_stop();
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while ch.is_running() {}
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// DMA will be stopped when transfer is dropped
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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@@ -468,26 +495,30 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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unreachable!();
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}
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// clear idle flag
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if enable_idle_line_detection {
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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if !enable_idle_line_detection {
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transfer.await;
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// enable idle interrupt
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r.cr1().modify(|w| {
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w.set_idleie(true);
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});
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return Ok(ReadCompletionEvent::DmaCompleted);
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}
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// clear idle flag
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let sr = sr(r).read();
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// This read also clears the error and idle interrupt flags on v1.
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rdr(r).read_volatile();
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clear_interrupt_flags(r, sr);
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// enable idle interrupt
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r.cr1().modify(|w| {
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w.set_idleie(true);
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});
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}
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compiler_fence(Ordering::SeqCst);
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let res = poll_fn(move |cx| {
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// future which completes when idle line is detected
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let idle = poll_fn(move |cx| {
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let s = T::state();
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ch.set_waker(cx.waker());
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s.rx_waker.register(cx.waker());
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// SAFETY: read only and we only use Rx related flags
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@@ -507,10 +538,6 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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if has_errors {
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// all Rx interrupts and Rx DMA Request have already been cleared in interrupt handler
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// stop dma transfer
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ch.request_stop();
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while ch.is_running() {}
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if sr.pe() {
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return Poll::Ready(Err(Error::Parity));
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}
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@@ -525,45 +552,54 @@ impl<'d, T: BasicInstance, RxDma> UartRx<'d, T, RxDma> {
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}
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}
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if enable_idle_line_detection && sr.idle() {
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// Idle line
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// stop dma transfer
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ch.request_stop();
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while ch.is_running() {}
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let n = buffer_len - (ch.remaining_transfers() as usize);
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return Poll::Ready(Ok(n));
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} else if !ch.is_running() {
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// DMA complete
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return Poll::Ready(Ok(buffer_len));
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if sr.idle() {
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// Idle line detected
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return Poll::Ready(Ok(()));
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}
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Poll::Pending
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})
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.await;
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});
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// clear all interrupts and DMA Rx Request
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// SAFETY: only clears Rx related flags
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unsafe {
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r.cr1().modify(|w| {
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// disable RXNE interrupt
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w.set_rxneie(false);
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// disable parity interrupt
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w.set_peie(false);
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// disable idle line interrupt
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w.set_idleie(false);
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});
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r.cr3().modify(|w| {
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// disable Error Interrupt: (Frame error, Noise error, Overrun error)
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w.set_eie(false);
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// disable DMA Rx Request
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w.set_dmar(false);
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});
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// wait for the first of DMA request or idle line detected to completes
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// select consumes its arguments
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// when transfer is dropped, it will stop the DMA request
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match select(transfer, idle).await {
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// DMA transfer completed first
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Either::First(()) => Ok(ReadCompletionEvent::DmaCompleted),
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// Idle line detected first
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Either::Second(Ok(())) => Ok(ReadCompletionEvent::Idle),
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// error occurred
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Either::Second(Err(e)) => Err(e),
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}
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}
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async fn inner_read(&mut self, buffer: &mut [u8], enable_idle_line_detection: bool) -> Result<usize, Error>
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where
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RxDma: crate::usart::RxDma<T>,
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{
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if buffer.is_empty() {
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return Ok(0);
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} else if buffer.len() > 0xFFFF {
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return Err(Error::BufferTooLong);
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}
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res
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let buffer_len = buffer.len();
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// wait for DMA to complete or IDLE line detection if requested
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let res = self.inner_read_run(buffer, enable_idle_line_detection).await;
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let ch = &mut self.rx_dma;
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match res {
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Ok(ReadCompletionEvent::DmaCompleted) => Ok(buffer_len),
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Ok(ReadCompletionEvent::Idle) => {
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let n = buffer_len - (ch.remaining_transfers() as usize);
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Ok(n)
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}
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Err(e) => Err(e),
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}
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}
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}
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