Merge branch 'stm32-neo'

.gitmodules

@@ -0,0 +1,3 @@
+[submodule "embassy-stm32/stm32-data"]
+	path = embassy-stm32/stm32-data
+	url = https://github.com/Dirbaio/stm32-data.git

.vscode/settings.json

@@ -1,7 +1,6 @@
 {
   "rust-analyzer.assist.importMergeBehavior": "last",
   "editor.formatOnSave": true,
-  "rust-analyzer.cargo.allFeatures": false,
   "rust-analyzer.checkOnSave.allFeatures": false,
   "rust-analyzer.checkOnSave.allTargets": false,
   "rust-analyzer.cargo.target": "thumbv7em-none-eabi",

embassy-macros/src/lib.rs

@@ -197,7 +197,7 @@ pub fn interrupt_declare(item: TokenStream) -> TokenStream {
             type Priority = crate::interrupt::Priority;
             fn number(&self) -> u16 {
                 use cortex_m::interrupt::InterruptNumber;
-                let irq = crate::pac::Interrupt::#name;
+                let irq = InterruptEnum::#name;
                 irq.number() as u16
             }
             unsafe fn steal() -> Self {

embassy-stm32-examples/Cargo.toml

@@ -0,0 +1,34 @@
+[package]
+authors = ["Dario Nieuwenhuis <dirbaio@dirbaio.net>"]
+edition = "2018"
+name = "embassy-stm32f4-examples"
+version = "0.1.0"
+
+[features]
+default = [
+    "defmt-default",
+]
+defmt-default = []
+defmt-trace = []
+defmt-debug = []
+defmt-info = []
+defmt-warn = []
+defmt-error = []
+
+[dependencies]
+embassy = { version = "0.1.0", path = "../embassy", features = ["defmt", "defmt-trace"] }
+embassy-traits = { version = "0.1.0", path = "../embassy-traits", features = ["defmt"] }
+embassy-stm32 = { version = "0.1.0", path = "../embassy-stm32", features = ["defmt", "defmt-trace", "stm32f429zi"]  }
+embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
+stm32f4 = { version = "0.13", features = ["stm32f429"] }
+
+defmt = "0.2.0"
+defmt-rtt = "0.2.0"
+
+cortex-m = "0.7.1"
+cortex-m-rt = "0.6.13"
+embedded-hal    = { version = "0.2.4" }
+panic-probe = { version = "0.2.0", features= ["print-defmt"] }
+futures = { version = "0.3.8", default-features = false, features = ["async-await"] }
+rtt-target = { version = "0.3", features = ["cortex-m"] }
+heapless = "0.7"

embassy-stm32-examples/src/bin/blinky.rs

@@ -0,0 +1,53 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use embassy_stm32::gpio::{Level, Output};
+use embedded_hal::digital::v2::OutputPin;
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32f4::stm32f429 as pac;
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w
+    });
+
+    let p = embassy_stm32::init(Default::default());
+
+    let mut led = Output::new(p.PB7, Level::High);
+
+    loop {
+        info!("high");
+        led.set_high().unwrap();
+        cortex_m::asm::delay(10_000_000);
+
+        info!("low");
+        led.set_low().unwrap();
+        cortex_m::asm::delay(10_000_000);
+    }
+}

embassy-stm32-examples/src/bin/button.rs

@@ -0,0 +1,58 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use embassy_stm32::gpio::{Input, Level, Output, Pull};
+use embedded_hal::digital::v2::{InputPin, OutputPin};
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32f4::stm32f429 as pac;
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w
+    });
+
+    let p = embassy_stm32::init(Default::default());
+
+    let button = Input::new(p.PC13, Pull::Down);
+    let mut led1 = Output::new(p.PB0, Level::High);
+    let _led2 = Output::new(p.PB7, Level::High);
+    let mut led3 = Output::new(p.PB14, Level::High);
+
+    loop {
+        if button.is_high().unwrap() {
+            info!("high");
+            led1.set_high().unwrap();
+            led3.set_low().unwrap();
+        } else {
+            info!("low");
+            led1.set_low().unwrap();
+            led3.set_high().unwrap();
+        }
+    }
+}

embassy-stm32-examples/src/bin/button_exti.rs

@@ -0,0 +1,82 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use embassy::executor::Executor;
+use embassy::time::Clock;
+use embassy::util::Forever;
+use embassy_stm32::exti::{self, ExtiInput};
+use embassy_stm32::gpio::{Input, Pull};
+use embassy_traits::gpio::{WaitForFallingEdge, WaitForRisingEdge};
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32f4::stm32f429 as pac;
+
+#[embassy::task]
+async fn main_task() {
+    let p = embassy_stm32::init(Default::default());
+
+    let button = Input::new(p.PC13, Pull::Down);
+    let mut button = ExtiInput::new(button, p.EXTI13);
+
+    info!("Press the USER button...");
+
+    loop {
+        button.wait_for_rising_edge().await;
+        info!("Pressed!");
+        button.wait_for_falling_edge().await;
+        info!("Released!");
+    }
+}
+
+struct ZeroClock;
+
+impl Clock for ZeroClock {
+    fn now(&self) -> u64 {
+        0
+    }
+}
+
+static EXECUTOR: Forever<Executor> = Forever::new();
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w
+    });
+    pp.RCC.apb2enr.modify(|_, w| {
+        w.syscfgen().enabled();
+        w
+    });
+
+    unsafe { embassy::time::set_clock(&ZeroClock) };
+
+    let executor = EXECUTOR.put(Executor::new());
+
+    executor.run(|spawner| {
+        unwrap!(spawner.spawn(main_task()));
+    })
+}

embassy-stm32-examples/src/bin/spi.rs

@@ -0,0 +1,72 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+
+use embassy_stm32::gpio::{Input, Level, Output, Pull};
+use embedded_hal::digital::v2::{InputPin, OutputPin};
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32f4::stm32f429 as pac;
+//use stm32l4::stm32l4x5 as pac;
+use embassy_stm32::spi::{ByteOrder, Config, Spi, MODE_0};
+use embassy_stm32::time::Hertz;
+use embedded_hal::blocking::spi::Transfer;
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World, dude!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().set_bit());
+
+    pp.RCC.apb1enr.modify(|_, w| {
+        w.spi3en().enabled();
+        w
+    });
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w
+    });
+
+    let rc = pp.RCC.cfgr.read().sws().bits();
+    let p = embassy_stm32::init(Default::default());
+
+    let mut spi = Spi::new(
+        Hertz(16_000_000),
+        p.SPI3,
+        p.PC10,
+        p.PC12,
+        p.PC11,
+        Hertz(1_000_000),
+        Config::default(),
+    );
+
+    let mut cs = Output::new(p.PE0, Level::High);
+
+    loop {
+        let mut buf = [0x0A; 4];
+        cs.set_low();
+        spi.transfer(&mut buf);
+        cs.set_high();
+        info!("xfer {=[u8]:x}", buf);
+    }
+}

embassy-stm32-examples/src/bin/usart.rs

@@ -0,0 +1,86 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use cortex_m::prelude::_embedded_hal_blocking_serial_Write;
+use embassy::executor::Executor;
+use embassy::time::Clock;
+use embassy::util::Forever;
+use embassy_stm32::gpio::NoPin;
+use embassy_stm32::usart::{Config, Uart};
+use example_common::*;
+
+use cortex_m_rt::entry;
+use stm32f4::stm32f429 as pac;
+
+#[embassy::task]
+async fn main_task() {
+    let p = embassy_stm32::init(Default::default());
+
+    let config = Config::default();
+    let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config, 16_000_000);
+
+    usart.bwrite_all(b"Hello Embassy World!\r\n").unwrap();
+    info!("wrote Hello, starting echo");
+
+    let mut buf = [0u8; 1];
+    loop {
+        usart.read(&mut buf).unwrap();
+        usart.bwrite_all(&buf).unwrap();
+    }
+}
+
+struct ZeroClock;
+
+impl Clock for ZeroClock {
+    fn now(&self) -> u64 {
+        0
+    }
+}
+
+static EXECUTOR: Forever<Executor> = Forever::new();
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w
+    });
+    pp.RCC.apb2enr.modify(|_, w| {
+        w.syscfgen().enabled();
+        w
+    });
+    pp.RCC.apb1enr.modify(|_, w| {
+        w.usart3en().enabled();
+        w
+    });
+
+    unsafe { embassy::time::set_clock(&ZeroClock) };
+
+    let executor = EXECUTOR.put(Executor::new());
+
+    executor.run(|spawner| {
+        unwrap!(spawner.spawn(main_task()));
+    })
+}

embassy-stm32-examples/src/bin/usart_dma.rs

@@ -0,0 +1,89 @@
+#![no_std]
+#![no_main]
+#![feature(trait_alias)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+
+#[path = "../example_common.rs"]
+mod example_common;
+use core::fmt::Write;
+use cortex_m_rt::entry;
+use embassy::executor::Executor;
+use embassy::time::Clock;
+use embassy::util::Forever;
+use embassy_stm32::usart::{Config, Uart};
+use example_common::*;
+use heapless::String;
+use stm32f4::stm32f429 as pac;
+
+#[embassy::task]
+async fn main_task() {
+    let mut p = embassy_stm32::init(Default::default());
+
+    let config = Config::default();
+    let mut usart = Uart::new(p.USART3, p.PD9, p.PD8, config, 16_000_000);
+
+    for n in 0.. {
+        let mut s: String<128> = String::new();
+        core::write!(&mut s, "Hello DMA World {}!\r\n", n).unwrap();
+
+        usart
+            .write_dma(&mut p.DMA1_CH3, s.as_bytes())
+            .await
+            .unwrap();
+        info!("wrote DMA");
+    }
+}
+
+struct ZeroClock;
+
+impl Clock for ZeroClock {
+    fn now(&self) -> u64 {
+        0
+    }
+}
+
+static EXECUTOR: Forever<Executor> = Forever::new();
+
+#[entry]
+fn main() -> ! {
+    info!("Hello World!");
+
+    let pp = pac::Peripherals::take().unwrap();
+
+    pp.DBGMCU.cr.modify(|_, w| {
+        w.dbg_sleep().set_bit();
+        w.dbg_standby().set_bit();
+        w.dbg_stop().set_bit()
+    });
+    pp.RCC.ahb1enr.modify(|_, w| w.dma1en().enabled());
+
+    pp.RCC.ahb1enr.modify(|_, w| {
+        w.gpioaen().enabled();
+        w.gpioben().enabled();
+        w.gpiocen().enabled();
+        w.gpioden().enabled();
+        w.gpioeen().enabled();
+        w.gpiofen().enabled();
+        w.dma1en().enabled();
+        w.dma2en().enabled();
+        w
+    });
+    pp.RCC.apb2enr.modify(|_, w| {
+        w.syscfgen().enabled();
+        w
+    });
+    pp.RCC.apb1enr.modify(|_, w| {
+        w.usart3en().enabled();
+        w
+    });
+
+    unsafe { embassy::time::set_clock(&ZeroClock) };
+
+    let executor = EXECUTOR.put(Executor::new());
+
+    executor.run(|spawner| {
+        unwrap!(spawner.spawn(main_task()));
+    })
+}

embassy-stm32/.pep8

@@ -0,0 +1,2 @@
+[pep8]
+max_line_length = 255

embassy-stm32/Cargo.toml

@@ -0,0 +1,463 @@
+[package]
+name = "embassy-stm32"
+version = "0.1.0"
+authors = ["Dario Nieuwenhuis <dirbaio@dirbaio.net>"]
+edition = "2018"
+
+[dependencies]
+embassy = { version = "0.1.0", path = "../embassy" }
+embassy-macros = { version = "0.1.0", path = "../embassy-macros" }
+embassy-extras = {version = "0.1.0", path = "../embassy-extras" }
+embassy-traits = {version = "0.1.0", path = "../embassy-traits" }
+
+defmt = { version = "0.2.0", optional = true }
+log = { version = "0.4.11", optional = true }
+cortex-m-rt = { version = "0.6.13", features = ["device"] }
+cortex-m = "0.7.1"
+embedded-hal    = { version = "0.2.4" }
+futures = { version = "0.3.5", default-features = false, features = ["async-await"] }
+rand_core = { version = "0.6.2", optional = true }
+sdio-host = { version = "0.5.0", optional = true }
+embedded-sdmmc = { git = "https://github.com/thalesfragoso/embedded-sdmmc-rs", branch = "async", optional = true }
+
+[build-dependencies]
+regex = "1.4.6"
+
+[features]
+defmt-trace = [ ]
+defmt-debug = [ ]
+defmt-info = [ ]
+defmt-warn = [ ]
+defmt-error = [ ]
+sdmmc-rs = ["embedded-sdmmc"]
+
+# BEGIN GENERATED FEATURES
+stm32f401cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401cd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401rd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401vd = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f401ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f405oe = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f405og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f405rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f405vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f405zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f407zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410c8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410cb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410r8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410t8 = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f410tb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411cc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f411ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412ce = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f412zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413cg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413mg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f413zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f415og = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f415rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f415vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f415zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f417zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f423ch = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f423mh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f423rh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f423vh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f423zh = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f427zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f429zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f437zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f439zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446mc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446me = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446rc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446vc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446zc = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f446ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_spi", "_spi_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469be = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ne = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f469zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32f479zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32f4", "_syscfg", "_syscfg_f4", "_usart", "_usart_v1",]
+stm32h723ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h723zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ae = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ie = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725re = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ve = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725ze = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h725zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h730zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h733vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h733zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h735zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h742zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h743zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h745zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747bg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747xg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h747zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750xb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h750zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h753zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h755zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757bi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757xi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h757zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ag = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ig = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3lg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ng = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3rg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3vg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3zg = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7a3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0ab = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0ib = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0rb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0vb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b0zb = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ai = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ii = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3li = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ni = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3qi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3ri = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3vi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32h7b3zi = [ "_dma", "_dma_v2", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_sdmmc", "_sdmmc_v2", "_stm32h7", "_syscfg", "_syscfg_h7",]
+stm32l412c8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412k8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412r8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412t8 = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l412tb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l422cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l422kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l422rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l422tb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l431vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l432kb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l432kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l433cb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l433cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l433rb = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l433rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l433vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l442kc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l443cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l443rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l443vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l451ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452cc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l452ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l462ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l462re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l462ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l471zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l475vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476je = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476jg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476me = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476mg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476rc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476vc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l476zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l485jc = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l485je = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l486jg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l486qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l486rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l486vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l486zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496wg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l496zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4a6ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4a6qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4a6rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4a6vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4a6zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4", "_syscfg", "_syscfg_l4", "_usart", "_usart_v2",]
+stm32l4p5ae = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5ce = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5qe = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5re = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5ve = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5ze = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4p5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5cg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5rg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4q5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5qg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9ag = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9vg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9zg = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4r9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s5ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s5qi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s5vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s5zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s7ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s7vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s7zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s9ai = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s9vi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+stm32l4s9zi = [ "_dma", "_dma_v1", "_exti", "_exti_v1", "_gpio", "_gpio_v2", "_rng", "_rng_v1", "_spi", "_spi_v2", "_stm32l4p", "_syscfg", "_syscfg_l4",]
+_dma = []
+_dma_v1 = []
+_dma_v2 = []
+_exti = []
+_exti_v1 = []
+_gpio = []
+_gpio_v2 = []
+_rng = [ "rand_core",]
+_rng_v1 = []
+_sdmmc = [ "sdio-host",]
+_sdmmc_v2 = []
+_spi = []
+_spi_v1 = []
+_spi_v2 = []
+_stm32f4 = []
+_stm32h7 = []
+_stm32l4 = []
+_stm32l4p = []
+_syscfg = []
+_syscfg_f4 = []
+_syscfg_h7 = []
+_syscfg_l4 = []
+_usart = []
+_usart_v1 = []
+_usart_v2 = []
+# END GENERATED FEATURES

embassy-stm32/build.rs

@@ -0,0 +1,34 @@
+use regex::Regex;
+use std::fmt::Write as _;
+use std::fs::File;
+use std::io::Write;
+use std::path::PathBuf;
+use std::{env, fs};
+
+fn main() {
+    let chip = env::vars_os()
+        .map(|(a, _)| a.to_string_lossy().to_string())
+        .find(|x| x.starts_with("CARGO_FEATURE_STM32"))
+        .expect("No stm32xx Cargo feature enabled")
+        .strip_prefix("CARGO_FEATURE_")
+        .unwrap()
+        .to_ascii_lowercase();
+
+    let mut device_x = String::new();
+
+    let chip_rs = fs::read_to_string(format!("src/pac/{}.rs", chip)).unwrap();
+    let re = Regex::new("declare!\\(([a-zA-Z0-9_]+)\\)").unwrap();
+    for c in re.captures_iter(&chip_rs) {
+        let name = c.get(1).unwrap().as_str();
+        write!(&mut device_x, "PROVIDE({} = DefaultHandler);\n", name).unwrap();
+    }
+
+    let out = &PathBuf::from(env::var_os("OUT_DIR").unwrap());
+    File::create(out.join("device.x"))
+        .unwrap()
+        .write_all(device_x.as_bytes())
+        .unwrap();
+    println!("cargo:rustc-link-search={}", out.display());
+    println!("cargo:rerun-if-changed=src/pac/{}.rs", chip);
+    println!("cargo:rerun-if-changed=build.rs");
+}

embassy-stm32/gen.py

@@ -0,0 +1,279 @@
+import xmltodict
+import yaml
+import re
+import json
+import os
+import toml
+from collections import OrderedDict
+from glob import glob
+
+abspath = os.path.abspath(__file__)
+dname = os.path.dirname(abspath)
+os.chdir(dname)
+
+# ======= load chips
+chips = {}
+for f in sorted(glob('stm32-data/data/chips/*.yaml')):
+    if 'STM32F4' not in f and 'STM32L4' not in f and 'STM32H7' not in f:
+        continue
+    with open(f, 'r') as f:
+        chip = yaml.load(f, Loader=yaml.CSafeLoader)
+    chip['name'] = chip['name'].lower()
+    chip['features'] = set()
+    family = chip["family"].lower().replace('+', 'p')
+    chip['features'].add(f'_{family}')
+    print(chip['name'])
+    chips[chip['name']] = chip
+
+# ======= load GPIO AF
+gpio_afs = {}
+for f in sorted(glob('stm32-data/data/gpio_af/*.yaml')):
+    name = f.split('/')[-1].split('.')[0]
+    with open(f, 'r') as f:
+        af = yaml.load(f, Loader=yaml.CSafeLoader)
+    gpio_afs[name] = af
+
+# ========= Generate pac/mod.rs
+
+with open('src/pac/mod.rs', 'w') as f:
+    for chip in chips.values():
+        f.write(
+            f'#[cfg_attr(feature="{chip["name"]}", path="{chip["name"]}.rs")]\n')
+    f.write('mod chip;\n')
+    f.write('pub use chip::*;\n')
+
+# ========= Generate pac/stm32xxx.rs
+
+for chip in chips.values():
+    print(f'generating {chip["name"]}')
+    with open(f'src/pac/{chip["name"]}.rs', 'w') as f:
+
+        f.write("""
+            #![allow(dead_code)]
+            #![allow(unused_imports)]
+            #![allow(non_snake_case)]
+        """)
+
+        af = gpio_afs[chip['gpio_af']]
+        peripheral_names = []  # USART1, PA5, EXTI8
+        peripheral_versions = {}  # usart -> v1, syscfg -> f4
+        pins = set()  # set of all present pins. PA4, PA5...
+
+        # TODO this should probably come from the yamls?
+        # We don't want to hardcode the EXTI peripheral addr
+
+        gpio_base = chip['peripherals']['GPIOA']['address']
+        gpio_stride = 0x400
+        f.write(f"""
+            pub fn GPIO(n: usize) -> gpio::Gpio {{
+                gpio::Gpio((0x{gpio_base:x} + 0x{gpio_stride:x}*n) as _)
+            }}
+        """)
+
+        # ========= peripherals
+
+        peripheral_names.extend((f'EXTI{x}' for x in range(16)))
+
+        for (name, peri) in chip['peripherals'].items():
+            if 'block' not in peri:
+                continue
+
+            block = peri['block']
+            block_mod, block_name = block.rsplit('/')
+            block_mod, block_version = block_mod.rsplit('_')
+            block_name = block_name.capitalize()
+
+            # Check all peripherals have the same version: it's not OK for the same chip to use both usart_v1 and usart_v2
+            if old_version := peripheral_versions.get(block_mod):
+                if old_version != block_version:
+                    raise Exception(f'Peripheral {block_mod} has two versions: {old_version} and {block_version}')
+            peripheral_versions[block_mod] = block_version
+
+            # Set features
+            chip['features'].add(f'_{block_mod}')
+            chip['features'].add(f'_{block_mod}_{block_version}')
+
+            f.write(f'pub const {name}: {block_mod}::{block_name} = {block_mod}::{block_name}(0x{peri["address"]:x} as _);')
+
+            custom_singletons = False
+
+            if block_mod == 'usart':
+                f.write(f'impl_usart!({name});')
+                for pin, funcs in af.items():
+                    if pin in pins:
+                        if func := funcs.get(f'{name}_RX'):
+                            f.write(f'impl_usart_pin!({name}, RxPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_TX'):
+                            f.write(f'impl_usart_pin!({name}, TxPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_CTS'):
+                            f.write(f'impl_usart_pin!({name}, CtsPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_RTS'):
+                            f.write(f'impl_usart_pin!({name}, RtsPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_CK'):
+                            f.write(f'impl_usart_pin!({name}, CkPin, {pin}, {func});')
+
+            if block_mod == 'rng':
+                if 'RNG' in chip['interrupts']:
+                    f.write(f'impl_rng!({name}, RNG);')
+                else:
+                    f.write(f'impl_rng!({name}, HASH_RNG);')
+
+            if block_mod == 'spi':
+                clock = peri['clock']
+                f.write(f'impl_spi!({name}, {clock});')
+                for pin, funcs in af.items():
+                    if pin in pins:
+                        if func := funcs.get(f'{name}_SCK'):
+                            f.write(f'impl_spi_pin!({name}, SckPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_MOSI'):
+                            f.write(f'impl_spi_pin!({name}, MosiPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_MISO'):
+                            f.write(f'impl_spi_pin!({name}, MisoPin, {pin}, {func});')
+
+            if block_mod == 'gpio':
+                custom_singletons = True
+                port = name[4:]
+                port_num = ord(port) - ord('A')
+
+                assert peri['address'] == gpio_base + gpio_stride*port_num
+
+                for pin_num in range(16):
+                    pin = f'P{port}{pin_num}'
+                    pins.add(pin)
+                    peripheral_names.append(pin)
+                    f.write(f'impl_gpio_pin!({pin}, {port_num}, {pin_num}, EXTI{pin_num});')
+
+            if block_mod == 'dma':
+                custom_singletons = True
+                dma_num = int(name[3:])-1  # substract 1 because we want DMA1=0, DMA2=1
+                for ch_num in range(8):
+                    channel = f'{name}_CH{ch_num}'
+                    peripheral_names.append(channel)
+                    f.write(f'impl_dma_channel!({channel}, {dma_num}, {ch_num});')
+
+            if peri['block'] == 'sdmmc_v2/SDMMC':
+                f.write(f'impl_sdmmc!({name});')
+                for pin, funcs in af.items():
+                    if pin in pins:
+                        if func := funcs.get(f'{name}_CK'):
+                            f.write(f'impl_sdmmc_pin!({name}, CkPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_CMD'):
+                            f.write(f'impl_sdmmc_pin!({name}, CmdPin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D0'):
+                            f.write(f'impl_sdmmc_pin!({name}, D0Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D1'):
+                            f.write(f'impl_sdmmc_pin!({name}, D1Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D2'):
+                            f.write(f'impl_sdmmc_pin!({name}, D2Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D3'):
+                            f.write(f'impl_sdmmc_pin!({name}, D3Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D4'):
+                            f.write(f'impl_sdmmc_pin!({name}, D4Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D5'):
+                            f.write(f'impl_sdmmc_pin!({name}, D5Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D6'):
+                            f.write(f'impl_sdmmc_pin!({name}, D6Pin, {pin}, {func});')
+                        if func := funcs.get(f'{name}_D7'):
+                            f.write(f'impl_sdmmc_pin!({name}, D7Pin, {pin}, {func});')
+
+            if not custom_singletons:
+                peripheral_names.append(name)
+
+        for mod, version in peripheral_versions.items():
+            f.write(f'pub use regs::{mod}_{version} as {mod};')
+
+        f.write(f"""
+            mod regs;
+            pub use regs::generic;
+            use embassy_extras::peripherals;
+            peripherals!({','.join(peripheral_names)});
+        """)
+
+        # ========= interrupts
+
+        irq_variants = []
+        irq_vectors = []
+        irq_fns = []
+        irq_declares = []
+
+        irqs = {num: name for name, num in chip['interrupts'].items()}
+        irq_count = max(irqs.keys()) + 1
+        for num, name in irqs.items():
+            irq_variants.append(f'{name} = {num},')
+            irq_fns.append(f'fn {name}();')
+            irq_declares.append(f'declare!({name});')
+        for num in range(irq_count):
+            if name := irqs.get(num):
+                irq_vectors.append(f'Vector {{ _handler: {name} }},')
+            else:
+                irq_vectors.append(f'Vector {{ _reserved: 0 }},')
+
+        f.write(f"""
+            pub mod interrupt {{
+                pub use cortex_m::interrupt::{{CriticalSection, Mutex}};
+                pub use embassy::interrupt::{{declare, take, Interrupt}};
+                pub use embassy_extras::interrupt::Priority4 as Priority;
+
+                #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+                #[allow(non_camel_case_types)]
+                pub enum InterruptEnum {{
+                    {''.join(irq_variants)}
+                }}
+                unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {{
+                    #[inline(always)]
+                    fn number(self) -> u16 {{
+                        self as u16
+                    }}
+                }}
+
+                {''.join(irq_declares)}
+            }}
+            mod interrupt_vector {{
+                extern "C" {{
+                    {''.join(irq_fns)} 
+                }}
+                pub union Vector {{
+                    _handler: unsafe extern "C" fn(),
+                    _reserved: u32,
+                }}
+                #[link_section = ".vector_table.interrupts"]
+                #[no_mangle]
+                pub static __INTERRUPTS: [Vector; {irq_count}] = [
+                    {''.join(irq_vectors)}
+                ];
+            }}
+        """)
+
+
+# ========= Update Cargo features
+
+feature_optional_deps = {}
+feature_optional_deps['_rng'] = ['rand_core']
+feature_optional_deps['_sdmmc'] = ['sdio-host']
+
+features = {}
+extra_features = set()
+for name, chip in chips.items():
+    features[name] = sorted(list(chip['features']))
+    for feature in chip['features']:
+        extra_features.add(feature)
+for feature in sorted(list(extra_features)):
+    features[feature] = feature_optional_deps.get(feature) or []
+
+SEPARATOR_START = '# BEGIN GENERATED FEATURES\n'
+SEPARATOR_END = '# END GENERATED FEATURES\n'
+
+with open('Cargo.toml', 'r') as f:
+    cargo = f.read()
+before, cargo = cargo.split(SEPARATOR_START, maxsplit=1)
+_, after = cargo.split(SEPARATOR_END, maxsplit=1)
+cargo = before + SEPARATOR_START + toml.dumps(features) + SEPARATOR_END + after
+with open('Cargo.toml', 'w') as f:
+    f.write(cargo)
+
+# ========= Generate pac/regs.rs
+os.system('cargo run --manifest-path ../../svd2rust/Cargo.toml -- generate --dir stm32-data/data/registers')
+os.system('mv lib.rs src/pac/regs.rs')
+
+# ========= Update Cargo features
+os.system('rustfmt src/pac/*')

embassy-stm32/src/dma/mod.rs

@@ -0,0 +1,44 @@
+#![macro_use]
+
+#[cfg_attr(feature = "_dma_v1", path = "v1.rs")]
+#[cfg_attr(feature = "_dma_v2", path = "v2.rs")]
+mod _version;
+pub use _version::*;
+
+use crate::pac;
+
+pub(crate) mod sealed {
+    use super::*;
+
+    pub trait Channel {
+        fn num(&self) -> u8;
+
+        fn dma_num(&self) -> u8 {
+            self.num() / 8
+        }
+        fn ch_num(&self) -> u8 {
+            self.num() % 8
+        }
+
+        fn regs(&self) -> pac::dma::Dma {
+            match self.dma_num() {
+                0 => pac::DMA1,
+                _ => pac::DMA2,
+            }
+        }
+    }
+}
+
+pub trait Channel: sealed::Channel + Sized {}
+
+macro_rules! impl_dma_channel {
+    ($type:ident, $dma_num:expr, $ch_num:expr) => {
+        impl crate::dma::Channel for peripherals::$type {}
+        impl crate::dma::sealed::Channel for peripherals::$type {
+            #[inline]
+            fn num(&self) -> u8 {
+                $dma_num * 8 + $ch_num
+            }
+        }
+    };
+}

embassy-stm32/src/dma/v1.rs

@@ -0,0 +1,2 @@
+/// safety: must be called only once
+pub(crate) unsafe fn init() {}

embassy-stm32/src/dma/v2.rs

@@ -0,0 +1,187 @@
+use core::sync::atomic::{AtomicU8, Ordering};
+use core::task::Poll;
+use embassy::interrupt::{Interrupt, InterruptExt};
+use embassy::util::AtomicWaker;
+use futures::future::poll_fn;
+
+use super::*;
+use crate::fmt::{assert, *};
+use crate::interrupt;
+use crate::pac;
+use crate::pac::dma::{regs, vals};
+
+const DMAS: [pac::dma::Dma; 2] = [pac::DMA1, pac::DMA2];
+
+const CH_COUNT: usize = 16;
+const CH_STATUS_NONE: u8 = 0;
+const CH_STATUS_COMPLETED: u8 = 1;
+const CH_STATUS_ERROR: u8 = 2;
+
+struct State {
+    ch_wakers: [AtomicWaker; CH_COUNT],
+    ch_status: [AtomicU8; CH_COUNT],
+}
+
+impl State {
+    const fn new() -> Self {
+        const AW: AtomicWaker = AtomicWaker::new();
+        const AU: AtomicU8 = AtomicU8::new(CH_STATUS_NONE);
+        Self {
+            ch_wakers: [AW; CH_COUNT],
+            ch_status: [AU; CH_COUNT],
+        }
+    }
+}
+
+static STATE: State = State::new();
+
+pub(crate) async unsafe fn transfer_m2p(
+    ch: &mut impl Channel,
+    ch_func: u8,
+    src: &[u8],
+    dst: *mut u8,
+) {
+    let n = ch.num() as usize;
+    let r = ch.regs();
+    let c = r.st(ch.ch_num() as _);
+
+    // ndtr is max 16 bits.
+    assert!(src.len() <= 0xFFFF);
+
+    // Reset status
+    STATE.ch_status[n].store(CH_STATUS_NONE, Ordering::Relaxed);
+
+    unsafe {
+        c.par().write_value(dst as _);
+        c.m0ar().write_value(src.as_ptr() as _);
+        c.ndtr().write_value(regs::Ndtr(src.len() as _));
+        c.cr().write(|w| {
+            w.set_dir(vals::Dir::MEMORYTOPERIPHERAL);
+            w.set_msize(vals::Size::BITS8);
+            w.set_psize(vals::Size::BITS8);
+            w.set_minc(vals::Inc::INCREMENTED);
+            w.set_pinc(vals::Inc::FIXED);
+            w.set_chsel(ch_func);
+            w.set_teie(true);
+            w.set_tcie(true);
+            w.set_en(true);
+        });
+    }
+
+    let res = poll_fn(|cx| {
+        STATE.ch_wakers[n].register(cx.waker());
+        match STATE.ch_status[n].load(Ordering::Relaxed) {
+            CH_STATUS_NONE => Poll::Pending,
+            x => Poll::Ready(x),
+        }
+    })
+    .await;
+
+    // TODO handle error
+    assert!(res == CH_STATUS_COMPLETED);
+}
+
+unsafe fn on_irq() {
+    for (dman, &dma) in DMAS.iter().enumerate() {
+        for isrn in 0..2 {
+            let isr = dma.isr(isrn).read();
+            dma.ifcr(isrn).write_value(isr);
+
+            for chn in 0..4 {
+                let n = dman * 8 + isrn * 4 + chn;
+                if isr.teif(chn) {
+                    STATE.ch_status[n].store(CH_STATUS_ERROR, Ordering::Relaxed);
+                    STATE.ch_wakers[n].wake();
+                } else if isr.tcif(chn) {
+                    STATE.ch_status[n].store(CH_STATUS_COMPLETED, Ordering::Relaxed);
+                    STATE.ch_wakers[n].wake();
+                }
+            }
+        }
+    }
+}
+
+#[interrupt]
+unsafe fn DMA1_Stream0() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream1() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream2() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream3() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream4() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream5() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream6() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA1_Stream7() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream0() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream1() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream2() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream3() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream4() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream5() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream6() {
+    on_irq()
+}
+#[interrupt]
+unsafe fn DMA2_Stream7() {
+    on_irq()
+}
+
+/// safety: must be called only once
+pub(crate) unsafe fn init() {
+    interrupt::DMA1_Stream0::steal().enable();
+    interrupt::DMA1_Stream1::steal().enable();
+    interrupt::DMA1_Stream2::steal().enable();
+    interrupt::DMA1_Stream3::steal().enable();
+    interrupt::DMA1_Stream4::steal().enable();
+    interrupt::DMA1_Stream5::steal().enable();
+    interrupt::DMA1_Stream6::steal().enable();
+    interrupt::DMA1_Stream7::steal().enable();
+    interrupt::DMA2_Stream0::steal().enable();
+    interrupt::DMA2_Stream1::steal().enable();
+    interrupt::DMA2_Stream2::steal().enable();
+    interrupt::DMA2_Stream3::steal().enable();
+    interrupt::DMA2_Stream4::steal().enable();
+    interrupt::DMA2_Stream5::steal().enable();
+    interrupt::DMA2_Stream6::steal().enable();
+    interrupt::DMA2_Stream7::steal().enable();
+}

embassy-stm32/src/exti.rs

@@ -0,0 +1,263 @@
+#![macro_use]
+use core::convert::Infallible;
+use core::future::Future;
+use core::marker::PhantomData;
+use core::pin::Pin;
+use core::task::{Context, Poll};
+use embassy::interrupt::{Interrupt, InterruptExt};
+use embassy::traits::gpio::{WaitForAnyEdge, WaitForFallingEdge, WaitForRisingEdge};
+use embassy::util::{AtomicWaker, Unborrow};
+use embassy_extras::impl_unborrow;
+use embedded_hal::digital::v2::InputPin;
+use pac::exti::{regs, vals};
+
+use crate::fmt::*;
+use crate::gpio::{AnyPin, Input, Pin as GpioPin};
+use crate::interrupt;
+use crate::pac;
+use crate::pac::{EXTI, SYSCFG};
+use crate::peripherals;
+
+const EXTI_COUNT: usize = 16;
+const NEW_AW: AtomicWaker = AtomicWaker::new();
+static EXTI_WAKERS: [AtomicWaker; EXTI_COUNT] = [NEW_AW; EXTI_COUNT];
+
+#[interrupt]
+unsafe fn EXTI0() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI1() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI2() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI3() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI4() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI9_5() {
+    on_irq()
+}
+
+#[interrupt]
+unsafe fn EXTI15_10() {
+    on_irq()
+}
+
+pub unsafe fn on_irq() {
+    let bits = EXTI.pr().read().0;
+
+    // Mask all the channels that fired.
+    EXTI.imr().modify(|w| w.0 &= !bits);
+
+    // Wake the tasks
+    for pin in BitIter(bits) {
+        EXTI_WAKERS[pin as usize].wake();
+    }
+
+    // Clear pending
+    EXTI.pr().write_value(regs::Pr(bits));
+}
+
+struct BitIter(u32);
+
+impl Iterator for BitIter {
+    type Item = u32;
+
+    fn next(&mut self) -> Option<Self::Item> {
+        match self.0.trailing_zeros() {
+            32 => None,
+            b => {
+                self.0 &= !(1 << b);
+                Some(b)
+            }
+        }
+    }
+}
+
+/// EXTI input driver
+pub struct ExtiInput<'d, T: GpioPin> {
+    pin: Input<'d, T>,
+}
+
+impl<'d, T: GpioPin> Unpin for ExtiInput<'d, T> {}
+
+impl<'d, T: GpioPin> ExtiInput<'d, T> {
+    pub fn new(pin: Input<'d, T>, _ch: impl Unborrow<Target = T::ExtiChannel> + 'd) -> Self {
+        Self { pin }
+    }
+}
+
+impl<'d, T: GpioPin> InputPin for ExtiInput<'d, T> {
+    type Error = Infallible;
+
+    fn is_high(&self) -> Result<bool, Self::Error> {
+        self.pin.is_high()
+    }
+
+    fn is_low(&self) -> Result<bool, Self::Error> {
+        self.pin.is_low()
+    }
+}
+
+impl<'d, T: GpioPin> WaitForRisingEdge for ExtiInput<'d, T> {
+    type Future<'a> = ExtiInputFuture<'a>;
+
+    fn wait_for_rising_edge<'a>(&'a mut self) -> Self::Future<'a> {
+        ExtiInputFuture::new(
+            self.pin.pin.pin(),
+            self.pin.pin.port(),
+            vals::Tr::ENABLED,
+            vals::Tr::DISABLED,
+        )
+    }
+}
+
+impl<'d, T: GpioPin> WaitForFallingEdge for ExtiInput<'d, T> {
+    type Future<'a> = ExtiInputFuture<'a>;
+
+    fn wait_for_falling_edge<'a>(&'a mut self) -> Self::Future<'a> {
+        ExtiInputFuture::new(
+            self.pin.pin.pin(),
+            self.pin.pin.port(),
+            vals::Tr::DISABLED,
+            vals::Tr::ENABLED,
+        )
+    }
+}
+
+impl<'d, T: GpioPin> WaitForAnyEdge for ExtiInput<'d, T> {
+    type Future<'a> = ExtiInputFuture<'a>;
+
+    fn wait_for_any_edge<'a>(&'a mut self) -> Self::Future<'a> {
+        ExtiInputFuture::new(
+            self.pin.pin.pin(),
+            self.pin.pin.port(),
+            vals::Tr::ENABLED,
+            vals::Tr::ENABLED,
+        )
+    }
+}
+
+pub struct ExtiInputFuture<'a> {
+    pin: u8,
+    phantom: PhantomData<&'a mut AnyPin>,
+}
+
+impl<'a> ExtiInputFuture<'a> {
+    fn new(pin: u8, port: u8, rising: vals::Tr, falling: vals::Tr) -> Self {
+        cortex_m::interrupt::free(|_| unsafe {
+            let pin = pin as usize;
+            SYSCFG.exticr(pin / 4).modify(|w| w.set_exti(pin % 4, port));
+            EXTI.rtsr().modify(|w| w.set_tr(pin, rising));
+            EXTI.ftsr().modify(|w| w.set_tr(pin, falling));
+            EXTI.pr().write(|w| w.set_pr(pin, true)); // clear pending bit
+            EXTI.imr().modify(|w| w.set_mr(pin, vals::Mr::UNMASKED));
+        });
+
+        Self {
+            pin,
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'a> Drop for ExtiInputFuture<'a> {
+    fn drop(&mut self) {
+        cortex_m::interrupt::free(|_| unsafe {
+            let pin = self.pin as _;
+            EXTI.imr().modify(|w| w.set_mr(pin, vals::Mr::MASKED));
+        });
+    }
+}
+
+impl<'a> Future for ExtiInputFuture<'a> {
+    type Output = ();
+
+    fn poll(self: Pin<&mut Self>, cx: &mut Context<'_>) -> Poll<Self::Output> {
+        EXTI_WAKERS[self.pin as usize].register(cx.waker());
+
+        if unsafe { EXTI.imr().read().mr(self.pin as _) == vals::Mr::MASKED } {
+            Poll::Ready(())
+        } else {
+            Poll::Pending
+        }
+    }
+}
+
+pub(crate) mod sealed {
+    pub trait Channel {}
+}
+
+pub trait Channel: sealed::Channel + Sized {
+    fn number(&self) -> usize;
+    fn degrade(self) -> AnyChannel {
+        AnyChannel {
+            number: self.number() as u8,
+        }
+    }
+}
+
+pub struct AnyChannel {
+    number: u8,
+}
+impl_unborrow!(AnyChannel);
+impl sealed::Channel for AnyChannel {}
+impl Channel for AnyChannel {
+    fn number(&self) -> usize {
+        self.number as usize
+    }
+}
+
+macro_rules! impl_exti {
+    ($type:ident, $number:expr) => {
+        impl sealed::Channel for peripherals::$type {}
+        impl Channel for peripherals::$type {
+            fn number(&self) -> usize {
+                $number as usize
+            }
+        }
+    };
+}
+
+impl_exti!(EXTI0, 0);
+impl_exti!(EXTI1, 1);
+impl_exti!(EXTI2, 2);
+impl_exti!(EXTI3, 3);
+impl_exti!(EXTI4, 4);
+impl_exti!(EXTI5, 5);
+impl_exti!(EXTI6, 6);
+impl_exti!(EXTI7, 7);
+impl_exti!(EXTI8, 8);
+impl_exti!(EXTI9, 9);
+impl_exti!(EXTI10, 10);
+impl_exti!(EXTI11, 11);
+impl_exti!(EXTI12, 12);
+impl_exti!(EXTI13, 13);
+impl_exti!(EXTI14, 14);
+impl_exti!(EXTI15, 15);
+
+/// safety: must be called only once
+pub(crate) unsafe fn init() {
+    interrupt::EXTI0::steal().enable();
+    interrupt::EXTI1::steal().enable();
+    interrupt::EXTI2::steal().enable();
+    interrupt::EXTI3::steal().enable();
+    interrupt::EXTI4::steal().enable();
+    interrupt::EXTI9_5::steal().enable();
+    interrupt::EXTI15_10::steal().enable();
+    interrupt::EXTI15_10::steal().enable();
+}

embassy-stm32/src/gpio.rs

@@ -0,0 +1,330 @@
+#![macro_use]
+use core::convert::Infallible;
+use core::marker::PhantomData;
+use embassy::util::Unborrow;
+use embassy_extras::{impl_unborrow, unborrow};
+use embedded_hal::digital::v2::{InputPin, OutputPin, StatefulOutputPin};
+
+use crate::pac;
+use crate::pac::gpio::{self, vals};
+
+/// Pull setting for an input.
+#[derive(Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Pull {
+    None,
+    Up,
+    Down,
+}
+
+/// GPIO input driver.
+pub struct Input<'d, T: Pin> {
+    pub(crate) pin: T,
+    phantom: PhantomData<&'d mut T>,
+}
+
+impl<'d, T: Pin> Input<'d, T> {
+    pub fn new(pin: impl Unborrow<Target = T> + 'd, pull: Pull) -> Self {
+        unborrow!(pin);
+
+        cortex_m::interrupt::free(|_| unsafe {
+            let r = pin.block();
+            let n = pin.pin() as usize;
+            let val = match pull {
+                Pull::None => vals::Pupdr::FLOATING,
+                Pull::Up => vals::Pupdr::PULLUP,
+                Pull::Down => vals::Pupdr::PULLDOWN,
+            };
+            r.pupdr().modify(|w| w.set_pupdr(n, val));
+            r.otyper().modify(|w| w.set_ot(n, vals::Ot::PUSHPULL));
+            r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
+        });
+
+        Self {
+            pin,
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'d, T: Pin> Drop for Input<'d, T> {
+    fn drop(&mut self) {
+        cortex_m::interrupt::free(|_| unsafe {
+            let r = self.pin.block();
+            let n = self.pin.pin() as usize;
+            r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
+        });
+    }
+}
+
+impl<'d, T: Pin> InputPin for Input<'d, T> {
+    type Error = Infallible;
+
+    fn is_high(&self) -> Result<bool, Self::Error> {
+        self.is_low().map(|v| !v)
+    }
+
+    fn is_low(&self) -> Result<bool, Self::Error> {
+        let state = unsafe { self.pin.block().idr().read().idr(self.pin.pin() as _) };
+        Ok(state == vals::Idr::LOW)
+    }
+}
+
+/// Digital input or output level.
+#[derive(Debug, Eq, PartialEq)]
+#[cfg_attr(feature = "defmt", derive(defmt::Format))]
+pub enum Level {
+    Low,
+    High,
+}
+
+/// GPIO output driver.
+pub struct Output<'d, T: Pin> {
+    pub(crate) pin: T,
+    phantom: PhantomData<&'d mut T>,
+}
+
+impl<'d, T: Pin> Output<'d, T> {
+    pub fn new(pin: impl Unborrow<Target = T> + 'd, initial_output: Level) -> Self {
+        unborrow!(pin);
+
+        match initial_output {
+            Level::High => pin.set_high(),
+            Level::Low => pin.set_low(),
+        }
+
+        cortex_m::interrupt::free(|_| unsafe {
+            let r = pin.block();
+            let n = pin.pin() as usize;
+            r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
+            r.moder().modify(|w| w.set_moder(n, vals::Moder::OUTPUT));
+        });
+
+        Self {
+            pin,
+            phantom: PhantomData,
+        }
+    }
+}
+
+impl<'d, T: Pin> Drop for Output<'d, T> {
+    fn drop(&mut self) {
+        cortex_m::interrupt::free(|_| unsafe {
+            let r = self.pin.block();
+            let n = self.pin.pin() as usize;
+            r.pupdr().modify(|w| w.set_pupdr(n, vals::Pupdr::FLOATING));
+            r.moder().modify(|w| w.set_moder(n, vals::Moder::INPUT));
+        });
+    }
+}
+
+impl<'d, T: Pin> OutputPin for Output<'d, T> {
+    type Error = Infallible;
+
+    /// Set the output as high.
+    fn set_high(&mut self) -> Result<(), Self::Error> {
+        self.pin.set_high();
+        Ok(())
+    }
+
+    /// Set the output as low.
+    fn set_low(&mut self) -> Result<(), Self::Error> {
+        self.pin.set_low();
+        Ok(())
+    }
+}
+
+impl<'d, T: Pin> StatefulOutputPin for Output<'d, T> {
+    /// Is the output pin set as high?
+    fn is_set_high(&self) -> Result<bool, Self::Error> {
+        self.is_set_low().map(|v| !v)
+    }
+
+    /// Is the output pin set as low?
+    fn is_set_low(&self) -> Result<bool, Self::Error> {
+        let state = unsafe { self.pin.block().odr().read().odr(self.pin.pin() as _) };
+        Ok(state == vals::Odr::LOW)
+    }
+}
+
+pub(crate) mod sealed {
+    use super::*;
+
+    pub trait Pin {
+        fn pin_port(&self) -> u8;
+
+        #[inline]
+        fn _pin(&self) -> u8 {
+            self.pin_port() % 16
+        }
+        #[inline]
+        fn _port(&self) -> u8 {
+            self.pin_port() / 16
+        }
+
+        #[inline]
+        fn block(&self) -> gpio::Gpio {
+            pac::GPIO(self._port() as _)
+        }
+
+        /// Set the output as high.
+        #[inline]
+        fn set_high(&self) {
+            unsafe {
+                let n = self._pin() as _;
+                self.block().bsrr().write(|w| w.set_bs(n, true));
+            }
+        }
+
+        /// Set the output as low.
+        #[inline]
+        fn set_low(&self) {
+            unsafe {
+                let n = self._pin() as _;
+                self.block().bsrr().write(|w| w.set_br(n, true));
+            }
+        }
+
+        unsafe fn set_as_af(&self, af_num: u8) {
+            let pin = self._pin() as usize;
+            let block = self.block();
+            block
+                .moder()
+                .modify(|w| w.set_moder(pin, vals::Moder::ALTERNATE));
+            block
+                .afr(pin / 8)
+                .modify(|w| w.set_afr(pin % 8, vals::Afr(af_num)));
+        }
+
+        unsafe fn set_as_analog(&self) {
+            let pin = self._pin() as usize;
+            let block = self.block();
+            block
+                .moder()
+                .modify(|w| w.set_moder(pin, vals::Moder::ANALOG));
+        }
+    }
+
+    pub trait OptionalPin {}
+}
+
+pub trait Pin: sealed::Pin + Sized {
+    type ExtiChannel: crate::exti::Channel;
+
+    /// Number of the pin within the port (0..31)
+    #[inline]
+    fn pin(&self) -> u8 {
+        self._pin()
+    }
+
+    /// Port of the pin
+    #[inline]
+    fn port(&self) -> u8 {
+        self._port()
+    }
+
+    /// Convert from concrete pin type PX_XX to type erased `AnyPin`.
+    #[inline]
+    fn degrade(self) -> AnyPin {
+        AnyPin {
+            pin_port: self.pin_port(),
+        }
+    }
+}
+
+// Type-erased GPIO pin
+pub struct AnyPin {
+    pin_port: u8,
+}
+
+impl AnyPin {
+    #[inline]
+    pub unsafe fn steal(pin_port: u8) -> Self {
+        Self { pin_port }
+    }
+
+    #[inline]
+    fn _port(&self) -> u8 {
+        self.pin_port / 16
+    }
+
+    #[inline]
+    pub fn block(&self) -> gpio::Gpio {
+        pac::GPIO(self._port() as _)
+    }
+}
+
+impl_unborrow!(AnyPin);
+impl Pin for AnyPin {
+    type ExtiChannel = crate::exti::AnyChannel;
+}
+impl sealed::Pin for AnyPin {
+    #[inline]
+    fn pin_port(&self) -> u8 {
+        self.pin_port
+    }
+}
+
+// ====================
+
+pub trait OptionalPin: sealed::OptionalPin + Sized {
+    type Pin: Pin;
+    fn pin(&self) -> Option<&Self::Pin>;
+    fn pin_mut(&mut self) -> Option<&mut Self::Pin>;
+
+    /// Convert from concrete pin type PX_XX to type erased `Option<AnyPin>`.
+    #[inline]
+    fn degrade_optional(mut self) -> Option<AnyPin> {
+        self.pin_mut()
+            .map(|pin| unsafe { core::ptr::read(pin) }.degrade())
+    }
+}
+
+impl<T: Pin> sealed::OptionalPin for T {}
+impl<T: Pin> OptionalPin for T {
+    type Pin = T;
+
+    #[inline]
+    fn pin(&self) -> Option<&T> {
+        Some(self)
+    }
+
+    #[inline]
+    fn pin_mut(&mut self) -> Option<&mut T> {
+        Some(self)
+    }
+}
+
+#[derive(Clone, Copy, Debug)]
+pub struct NoPin;
+impl_unborrow!(NoPin);
+impl sealed::OptionalPin for NoPin {}
+impl OptionalPin for NoPin {
+    type Pin = AnyPin;
+
+    #[inline]
+    fn pin(&self) -> Option<&AnyPin> {
+        None
+    }
+
+    #[inline]
+    fn pin_mut(&mut self) -> Option<&mut AnyPin> {
+        None
+    }
+}
+
+// ====================
+
+macro_rules! impl_gpio_pin {
+    ($type:ident, $port_num:expr, $pin_num:expr, $exti_ch:ident) => {
+        impl crate::gpio::Pin for peripherals::$type {
+            type ExtiChannel = peripherals::$exti_ch;
+        }
+        impl crate::gpio::sealed::Pin for peripherals::$type {
+            #[inline]
+            fn pin_port(&self) -> u8 {
+                $port_num * 16 + $pin_num
+            }
+        }
+    };
+}

embassy-stm32/src/lib.rs

@@ -0,0 +1,59 @@
+#![no_std]
+#![feature(generic_associated_types)]
+#![feature(asm)]
+#![feature(min_type_alias_impl_trait)]
+#![feature(impl_trait_in_bindings)]
+#![feature(type_alias_impl_trait)]
+#![allow(incomplete_features)]
+
+// This must go FIRST so that all the other modules see its macros.
+pub mod fmt;
+
+use embassy::interrupt::{Interrupt, InterruptExt};
+
+#[cfg(feature = "_dma")]
+pub mod dma;
+pub mod exti;
+pub mod gpio;
+#[cfg(feature = "_rng")]
+pub mod rng;
+#[cfg(feature = "_sdmmc")]
+pub mod sdmmc;
+#[cfg(feature = "_spi")]
+pub mod spi;
+#[cfg(feature = "_usart")]
+pub mod usart;
+
+// This must go LAST so that it sees the `impl_foo!` macros
+mod pac;
+
+pub mod time;
+
+pub use embassy_macros::interrupt;
+pub use pac::{interrupt, peripherals, Peripherals};
+
+// workaround for svd2rust-generated code using `use crate::generic::*;`
+pub(crate) use pac::generic;
+
+#[non_exhaustive]
+pub struct Config {
+    _private: (),
+}
+
+impl Default for Config {
+    fn default() -> Self {
+        Self { _private: () }
+    }
+}
+
+/// Initialize embassy.
+pub fn init(_config: Config) -> Peripherals {
+    let p = Peripherals::take();
+
+    unsafe {
+        exti::init();
+        dma::init();
+    }
+
+    p
+}

embassy-stm32/src/pac/mod.rs

@@ -0,0 +1,405 @@
+#[cfg_attr(feature = "stm32f401cb", path = "stm32f401cb.rs")]
+#[cfg_attr(feature = "stm32f401cc", path = "stm32f401cc.rs")]
+#[cfg_attr(feature = "stm32f401cd", path = "stm32f401cd.rs")]
+#[cfg_attr(feature = "stm32f401ce", path = "stm32f401ce.rs")]
+#[cfg_attr(feature = "stm32f401rb", path = "stm32f401rb.rs")]
+#[cfg_attr(feature = "stm32f401rc", path = "stm32f401rc.rs")]
+#[cfg_attr(feature = "stm32f401rd", path = "stm32f401rd.rs")]
+#[cfg_attr(feature = "stm32f401re", path = "stm32f401re.rs")]
+#[cfg_attr(feature = "stm32f401vb", path = "stm32f401vb.rs")]
+#[cfg_attr(feature = "stm32f401vc", path = "stm32f401vc.rs")]
+#[cfg_attr(feature = "stm32f401vd", path = "stm32f401vd.rs")]
+#[cfg_attr(feature = "stm32f401ve", path = "stm32f401ve.rs")]
+#[cfg_attr(feature = "stm32f405oe", path = "stm32f405oe.rs")]
+#[cfg_attr(feature = "stm32f405og", path = "stm32f405og.rs")]
+#[cfg_attr(feature = "stm32f405rg", path = "stm32f405rg.rs")]
+#[cfg_attr(feature = "stm32f405vg", path = "stm32f405vg.rs")]
+#[cfg_attr(feature = "stm32f405zg", path = "stm32f405zg.rs")]
+#[cfg_attr(feature = "stm32f407ie", path = "stm32f407ie.rs")]
+#[cfg_attr(feature = "stm32f407ig", path = "stm32f407ig.rs")]
+#[cfg_attr(feature = "stm32f407ve", path = "stm32f407ve.rs")]
+#[cfg_attr(feature = "stm32f407vg", path = "stm32f407vg.rs")]
+#[cfg_attr(feature = "stm32f407ze", path = "stm32f407ze.rs")]
+#[cfg_attr(feature = "stm32f407zg", path = "stm32f407zg.rs")]
+#[cfg_attr(feature = "stm32f410c8", path = "stm32f410c8.rs")]
+#[cfg_attr(feature = "stm32f410cb", path = "stm32f410cb.rs")]
+#[cfg_attr(feature = "stm32f410r8", path = "stm32f410r8.rs")]
+#[cfg_attr(feature = "stm32f410rb", path = "stm32f410rb.rs")]
+#[cfg_attr(feature = "stm32f410t8", path = "stm32f410t8.rs")]
+#[cfg_attr(feature = "stm32f410tb", path = "stm32f410tb.rs")]
+#[cfg_attr(feature = "stm32f411cc", path = "stm32f411cc.rs")]
+#[cfg_attr(feature = "stm32f411ce", path = "stm32f411ce.rs")]
+#[cfg_attr(feature = "stm32f411rc", path = "stm32f411rc.rs")]
+#[cfg_attr(feature = "stm32f411re", path = "stm32f411re.rs")]
+#[cfg_attr(feature = "stm32f411vc", path = "stm32f411vc.rs")]
+#[cfg_attr(feature = "stm32f411ve", path = "stm32f411ve.rs")]
+#[cfg_attr(feature = "stm32f412ce", path = "stm32f412ce.rs")]
+#[cfg_attr(feature = "stm32f412cg", path = "stm32f412cg.rs")]
+#[cfg_attr(feature = "stm32f412re", path = "stm32f412re.rs")]
+#[cfg_attr(feature = "stm32f412rg", path = "stm32f412rg.rs")]
+#[cfg_attr(feature = "stm32f412ve", path = "stm32f412ve.rs")]
+#[cfg_attr(feature = "stm32f412vg", path = "stm32f412vg.rs")]
+#[cfg_attr(feature = "stm32f412ze", path = "stm32f412ze.rs")]
+#[cfg_attr(feature = "stm32f412zg", path = "stm32f412zg.rs")]
+#[cfg_attr(feature = "stm32f413cg", path = "stm32f413cg.rs")]
+#[cfg_attr(feature = "stm32f413ch", path = "stm32f413ch.rs")]
+#[cfg_attr(feature = "stm32f413mg", path = "stm32f413mg.rs")]
+#[cfg_attr(feature = "stm32f413mh", path = "stm32f413mh.rs")]
+#[cfg_attr(feature = "stm32f413rg", path = "stm32f413rg.rs")]
+#[cfg_attr(feature = "stm32f413rh", path = "stm32f413rh.rs")]
+#[cfg_attr(feature = "stm32f413vg", path = "stm32f413vg.rs")]
+#[cfg_attr(feature = "stm32f413vh", path = "stm32f413vh.rs")]
+#[cfg_attr(feature = "stm32f413zg", path = "stm32f413zg.rs")]
+#[cfg_attr(feature = "stm32f413zh", path = "stm32f413zh.rs")]
+#[cfg_attr(feature = "stm32f415og", path = "stm32f415og.rs")]
+#[cfg_attr(feature = "stm32f415rg", path = "stm32f415rg.rs")]
+#[cfg_attr(feature = "stm32f415vg", path = "stm32f415vg.rs")]
+#[cfg_attr(feature = "stm32f415zg", path = "stm32f415zg.rs")]
+#[cfg_attr(feature = "stm32f417ie", path = "stm32f417ie.rs")]
+#[cfg_attr(feature = "stm32f417ig", path = "stm32f417ig.rs")]
+#[cfg_attr(feature = "stm32f417ve", path = "stm32f417ve.rs")]
+#[cfg_attr(feature = "stm32f417vg", path = "stm32f417vg.rs")]
+#[cfg_attr(feature = "stm32f417ze", path = "stm32f417ze.rs")]
+#[cfg_attr(feature = "stm32f417zg", path = "stm32f417zg.rs")]
+#[cfg_attr(feature = "stm32f423ch", path = "stm32f423ch.rs")]
+#[cfg_attr(feature = "stm32f423mh", path = "stm32f423mh.rs")]
+#[cfg_attr(feature = "stm32f423rh", path = "stm32f423rh.rs")]
+#[cfg_attr(feature = "stm32f423vh", path = "stm32f423vh.rs")]
+#[cfg_attr(feature = "stm32f423zh", path = "stm32f423zh.rs")]
+#[cfg_attr(feature = "stm32f427ag", path = "stm32f427ag.rs")]
+#[cfg_attr(feature = "stm32f427ai", path = "stm32f427ai.rs")]
+#[cfg_attr(feature = "stm32f427ig", path = "stm32f427ig.rs")]
+#[cfg_attr(feature = "stm32f427ii", path = "stm32f427ii.rs")]
+#[cfg_attr(feature = "stm32f427vg", path = "stm32f427vg.rs")]
+#[cfg_attr(feature = "stm32f427vi", path = "stm32f427vi.rs")]
+#[cfg_attr(feature = "stm32f427zg", path = "stm32f427zg.rs")]
+#[cfg_attr(feature = "stm32f427zi", path = "stm32f427zi.rs")]
+#[cfg_attr(feature = "stm32f429ag", path = "stm32f429ag.rs")]
+#[cfg_attr(feature = "stm32f429ai", path = "stm32f429ai.rs")]
+#[cfg_attr(feature = "stm32f429be", path = "stm32f429be.rs")]
+#[cfg_attr(feature = "stm32f429bg", path = "stm32f429bg.rs")]
+#[cfg_attr(feature = "stm32f429bi", path = "stm32f429bi.rs")]
+#[cfg_attr(feature = "stm32f429ie", path = "stm32f429ie.rs")]
+#[cfg_attr(feature = "stm32f429ig", path = "stm32f429ig.rs")]
+#[cfg_attr(feature = "stm32f429ii", path = "stm32f429ii.rs")]
+#[cfg_attr(feature = "stm32f429ne", path = "stm32f429ne.rs")]
+#[cfg_attr(feature = "stm32f429ng", path = "stm32f429ng.rs")]
+#[cfg_attr(feature = "stm32f429ni", path = "stm32f429ni.rs")]
+#[cfg_attr(feature = "stm32f429ve", path = "stm32f429ve.rs")]
+#[cfg_attr(feature = "stm32f429vg", path = "stm32f429vg.rs")]
+#[cfg_attr(feature = "stm32f429vi", path = "stm32f429vi.rs")]
+#[cfg_attr(feature = "stm32f429ze", path = "stm32f429ze.rs")]
+#[cfg_attr(feature = "stm32f429zg", path = "stm32f429zg.rs")]
+#[cfg_attr(feature = "stm32f429zi", path = "stm32f429zi.rs")]
+#[cfg_attr(feature = "stm32f437ai", path = "stm32f437ai.rs")]
+#[cfg_attr(feature = "stm32f437ig", path = "stm32f437ig.rs")]
+#[cfg_attr(feature = "stm32f437ii", path = "stm32f437ii.rs")]
+#[cfg_attr(feature = "stm32f437vg", path = "stm32f437vg.rs")]
+#[cfg_attr(feature = "stm32f437vi", path = "stm32f437vi.rs")]
+#[cfg_attr(feature = "stm32f437zg", path = "stm32f437zg.rs")]
+#[cfg_attr(feature = "stm32f437zi", path = "stm32f437zi.rs")]
+#[cfg_attr(feature = "stm32f439ai", path = "stm32f439ai.rs")]
+#[cfg_attr(feature = "stm32f439bg", path = "stm32f439bg.rs")]
+#[cfg_attr(feature = "stm32f439bi", path = "stm32f439bi.rs")]
+#[cfg_attr(feature = "stm32f439ig", path = "stm32f439ig.rs")]
+#[cfg_attr(feature = "stm32f439ii", path = "stm32f439ii.rs")]
+#[cfg_attr(feature = "stm32f439ng", path = "stm32f439ng.rs")]
+#[cfg_attr(feature = "stm32f439ni", path = "stm32f439ni.rs")]
+#[cfg_attr(feature = "stm32f439vg", path = "stm32f439vg.rs")]
+#[cfg_attr(feature = "stm32f439vi", path = "stm32f439vi.rs")]
+#[cfg_attr(feature = "stm32f439zg", path = "stm32f439zg.rs")]
+#[cfg_attr(feature = "stm32f439zi", path = "stm32f439zi.rs")]
+#[cfg_attr(feature = "stm32f446mc", path = "stm32f446mc.rs")]
+#[cfg_attr(feature = "stm32f446me", path = "stm32f446me.rs")]
+#[cfg_attr(feature = "stm32f446rc", path = "stm32f446rc.rs")]
+#[cfg_attr(feature = "stm32f446re", path = "stm32f446re.rs")]
+#[cfg_attr(feature = "stm32f446vc", path = "stm32f446vc.rs")]
+#[cfg_attr(feature = "stm32f446ve", path = "stm32f446ve.rs")]
+#[cfg_attr(feature = "stm32f446zc", path = "stm32f446zc.rs")]
+#[cfg_attr(feature = "stm32f446ze", path = "stm32f446ze.rs")]
+#[cfg_attr(feature = "stm32f469ae", path = "stm32f469ae.rs")]
+#[cfg_attr(feature = "stm32f469ag", path = "stm32f469ag.rs")]
+#[cfg_attr(feature = "stm32f469ai", path = "stm32f469ai.rs")]
+#[cfg_attr(feature = "stm32f469be", path = "stm32f469be.rs")]
+#[cfg_attr(feature = "stm32f469bg", path = "stm32f469bg.rs")]
+#[cfg_attr(feature = "stm32f469bi", path = "stm32f469bi.rs")]
+#[cfg_attr(feature = "stm32f469ie", path = "stm32f469ie.rs")]
+#[cfg_attr(feature = "stm32f469ig", path = "stm32f469ig.rs")]
+#[cfg_attr(feature = "stm32f469ii", path = "stm32f469ii.rs")]
+#[cfg_attr(feature = "stm32f469ne", path = "stm32f469ne.rs")]
+#[cfg_attr(feature = "stm32f469ng", path = "stm32f469ng.rs")]
+#[cfg_attr(feature = "stm32f469ni", path = "stm32f469ni.rs")]
+#[cfg_attr(feature = "stm32f469ve", path = "stm32f469ve.rs")]
+#[cfg_attr(feature = "stm32f469vg", path = "stm32f469vg.rs")]
+#[cfg_attr(feature = "stm32f469vi", path = "stm32f469vi.rs")]
+#[cfg_attr(feature = "stm32f469ze", path = "stm32f469ze.rs")]
+#[cfg_attr(feature = "stm32f469zg", path = "stm32f469zg.rs")]
+#[cfg_attr(feature = "stm32f469zi", path = "stm32f469zi.rs")]
+#[cfg_attr(feature = "stm32f479ag", path = "stm32f479ag.rs")]
+#[cfg_attr(feature = "stm32f479ai", path = "stm32f479ai.rs")]
+#[cfg_attr(feature = "stm32f479bg", path = "stm32f479bg.rs")]
+#[cfg_attr(feature = "stm32f479bi", path = "stm32f479bi.rs")]
+#[cfg_attr(feature = "stm32f479ig", path = "stm32f479ig.rs")]
+#[cfg_attr(feature = "stm32f479ii", path = "stm32f479ii.rs")]
+#[cfg_attr(feature = "stm32f479ng", path = "stm32f479ng.rs")]
+#[cfg_attr(feature = "stm32f479ni", path = "stm32f479ni.rs")]
+#[cfg_attr(feature = "stm32f479vg", path = "stm32f479vg.rs")]
+#[cfg_attr(feature = "stm32f479vi", path = "stm32f479vi.rs")]
+#[cfg_attr(feature = "stm32f479zg", path = "stm32f479zg.rs")]
+#[cfg_attr(feature = "stm32f479zi", path = "stm32f479zi.rs")]
+#[cfg_attr(feature = "stm32h723ve", path = "stm32h723ve.rs")]
+#[cfg_attr(feature = "stm32h723vg", path = "stm32h723vg.rs")]
+#[cfg_attr(feature = "stm32h723ze", path = "stm32h723ze.rs")]
+#[cfg_attr(feature = "stm32h723zg", path = "stm32h723zg.rs")]
+#[cfg_attr(feature = "stm32h725ae", path = "stm32h725ae.rs")]
+#[cfg_attr(feature = "stm32h725ag", path = "stm32h725ag.rs")]
+#[cfg_attr(feature = "stm32h725ie", path = "stm32h725ie.rs")]
+#[cfg_attr(feature = "stm32h725ig", path = "stm32h725ig.rs")]
+#[cfg_attr(feature = "stm32h725re", path = "stm32h725re.rs")]
+#[cfg_attr(feature = "stm32h725rg", path = "stm32h725rg.rs")]
+#[cfg_attr(feature = "stm32h725ve", path = "stm32h725ve.rs")]
+#[cfg_attr(feature = "stm32h725vg", path = "stm32h725vg.rs")]
+#[cfg_attr(feature = "stm32h725ze", path = "stm32h725ze.rs")]
+#[cfg_attr(feature = "stm32h725zg", path = "stm32h725zg.rs")]
+#[cfg_attr(feature = "stm32h730ab", path = "stm32h730ab.rs")]
+#[cfg_attr(feature = "stm32h730ib", path = "stm32h730ib.rs")]
+#[cfg_attr(feature = "stm32h730vb", path = "stm32h730vb.rs")]
+#[cfg_attr(feature = "stm32h730zb", path = "stm32h730zb.rs")]
+#[cfg_attr(feature = "stm32h733vg", path = "stm32h733vg.rs")]
+#[cfg_attr(feature = "stm32h733zg", path = "stm32h733zg.rs")]
+#[cfg_attr(feature = "stm32h735ag", path = "stm32h735ag.rs")]
+#[cfg_attr(feature = "stm32h735ig", path = "stm32h735ig.rs")]
+#[cfg_attr(feature = "stm32h735rg", path = "stm32h735rg.rs")]
+#[cfg_attr(feature = "stm32h735vg", path = "stm32h735vg.rs")]
+#[cfg_attr(feature = "stm32h735zg", path = "stm32h735zg.rs")]
+#[cfg_attr(feature = "stm32h742ag", path = "stm32h742ag.rs")]
+#[cfg_attr(feature = "stm32h742ai", path = "stm32h742ai.rs")]
+#[cfg_attr(feature = "stm32h742bg", path = "stm32h742bg.rs")]
+#[cfg_attr(feature = "stm32h742bi", path = "stm32h742bi.rs")]
+#[cfg_attr(feature = "stm32h742ig", path = "stm32h742ig.rs")]
+#[cfg_attr(feature = "stm32h742ii", path = "stm32h742ii.rs")]
+#[cfg_attr(feature = "stm32h742vg", path = "stm32h742vg.rs")]
+#[cfg_attr(feature = "stm32h742vi", path = "stm32h742vi.rs")]
+#[cfg_attr(feature = "stm32h742xg", path = "stm32h742xg.rs")]
+#[cfg_attr(feature = "stm32h742xi", path = "stm32h742xi.rs")]
+#[cfg_attr(feature = "stm32h742zg", path = "stm32h742zg.rs")]
+#[cfg_attr(feature = "stm32h742zi", path = "stm32h742zi.rs")]
+#[cfg_attr(feature = "stm32h743ag", path = "stm32h743ag.rs")]
+#[cfg_attr(feature = "stm32h743ai", path = "stm32h743ai.rs")]
+#[cfg_attr(feature = "stm32h743bg", path = "stm32h743bg.rs")]
+#[cfg_attr(feature = "stm32h743bi", path = "stm32h743bi.rs")]
+#[cfg_attr(feature = "stm32h743ig", path = "stm32h743ig.rs")]
+#[cfg_attr(feature = "stm32h743ii", path = "stm32h743ii.rs")]
+#[cfg_attr(feature = "stm32h743vg", path = "stm32h743vg.rs")]
+#[cfg_attr(feature = "stm32h743vi", path = "stm32h743vi.rs")]
+#[cfg_attr(feature = "stm32h743xg", path = "stm32h743xg.rs")]
+#[cfg_attr(feature = "stm32h743xi", path = "stm32h743xi.rs")]
+#[cfg_attr(feature = "stm32h743zg", path = "stm32h743zg.rs")]
+#[cfg_attr(feature = "stm32h743zi", path = "stm32h743zi.rs")]
+#[cfg_attr(feature = "stm32h745bg", path = "stm32h745bg.rs")]
+#[cfg_attr(feature = "stm32h745bi", path = "stm32h745bi.rs")]
+#[cfg_attr(feature = "stm32h745ig", path = "stm32h745ig.rs")]
+#[cfg_attr(feature = "stm32h745ii", path = "stm32h745ii.rs")]
+#[cfg_attr(feature = "stm32h745xg", path = "stm32h745xg.rs")]
+#[cfg_attr(feature = "stm32h745xi", path = "stm32h745xi.rs")]
+#[cfg_attr(feature = "stm32h745zg", path = "stm32h745zg.rs")]
+#[cfg_attr(feature = "stm32h745zi", path = "stm32h745zi.rs")]
+#[cfg_attr(feature = "stm32h747ag", path = "stm32h747ag.rs")]
+#[cfg_attr(feature = "stm32h747ai", path = "stm32h747ai.rs")]
+#[cfg_attr(feature = "stm32h747bg", path = "stm32h747bg.rs")]
+#[cfg_attr(feature = "stm32h747bi", path = "stm32h747bi.rs")]
+#[cfg_attr(feature = "stm32h747ig", path = "stm32h747ig.rs")]
+#[cfg_attr(feature = "stm32h747ii", path = "stm32h747ii.rs")]
+#[cfg_attr(feature = "stm32h747xg", path = "stm32h747xg.rs")]
+#[cfg_attr(feature = "stm32h747xi", path = "stm32h747xi.rs")]
+#[cfg_attr(feature = "stm32h747zi", path = "stm32h747zi.rs")]
+#[cfg_attr(feature = "stm32h750ib", path = "stm32h750ib.rs")]
+#[cfg_attr(feature = "stm32h750vb", path = "stm32h750vb.rs")]
+#[cfg_attr(feature = "stm32h750xb", path = "stm32h750xb.rs")]
+#[cfg_attr(feature = "stm32h750zb", path = "stm32h750zb.rs")]
+#[cfg_attr(feature = "stm32h753ai", path = "stm32h753ai.rs")]
+#[cfg_attr(feature = "stm32h753bi", path = "stm32h753bi.rs")]
+#[cfg_attr(feature = "stm32h753ii", path = "stm32h753ii.rs")]
+#[cfg_attr(feature = "stm32h753vi", path = "stm32h753vi.rs")]
+#[cfg_attr(feature = "stm32h753xi", path = "stm32h753xi.rs")]
+#[cfg_attr(feature = "stm32h753zi", path = "stm32h753zi.rs")]
+#[cfg_attr(feature = "stm32h755bi", path = "stm32h755bi.rs")]
+#[cfg_attr(feature = "stm32h755ii", path = "stm32h755ii.rs")]
+#[cfg_attr(feature = "stm32h755xi", path = "stm32h755xi.rs")]
+#[cfg_attr(feature = "stm32h755zi", path = "stm32h755zi.rs")]
+#[cfg_attr(feature = "stm32h757ai", path = "stm32h757ai.rs")]
+#[cfg_attr(feature = "stm32h757bi", path = "stm32h757bi.rs")]
+#[cfg_attr(feature = "stm32h757ii", path = "stm32h757ii.rs")]
+#[cfg_attr(feature = "stm32h757xi", path = "stm32h757xi.rs")]
+#[cfg_attr(feature = "stm32h757zi", path = "stm32h757zi.rs")]
+#[cfg_attr(feature = "stm32h7a3ag", path = "stm32h7a3ag.rs")]
+#[cfg_attr(feature = "stm32h7a3ai", path = "stm32h7a3ai.rs")]
+#[cfg_attr(feature = "stm32h7a3ig", path = "stm32h7a3ig.rs")]
+#[cfg_attr(feature = "stm32h7a3ii", path = "stm32h7a3ii.rs")]
+#[cfg_attr(feature = "stm32h7a3lg", path = "stm32h7a3lg.rs")]
+#[cfg_attr(feature = "stm32h7a3li", path = "stm32h7a3li.rs")]
+#[cfg_attr(feature = "stm32h7a3ng", path = "stm32h7a3ng.rs")]
+#[cfg_attr(feature = "stm32h7a3ni", path = "stm32h7a3ni.rs")]
+#[cfg_attr(feature = "stm32h7a3qi", path = "stm32h7a3qi.rs")]
+#[cfg_attr(feature = "stm32h7a3rg", path = "stm32h7a3rg.rs")]
+#[cfg_attr(feature = "stm32h7a3ri", path = "stm32h7a3ri.rs")]
+#[cfg_attr(feature = "stm32h7a3vg", path = "stm32h7a3vg.rs")]
+#[cfg_attr(feature = "stm32h7a3vi", path = "stm32h7a3vi.rs")]
+#[cfg_attr(feature = "stm32h7a3zg", path = "stm32h7a3zg.rs")]
+#[cfg_attr(feature = "stm32h7a3zi", path = "stm32h7a3zi.rs")]
+#[cfg_attr(feature = "stm32h7b0ab", path = "stm32h7b0ab.rs")]
+#[cfg_attr(feature = "stm32h7b0ib", path = "stm32h7b0ib.rs")]
+#[cfg_attr(feature = "stm32h7b0rb", path = "stm32h7b0rb.rs")]
+#[cfg_attr(feature = "stm32h7b0vb", path = "stm32h7b0vb.rs")]
+#[cfg_attr(feature = "stm32h7b0zb", path = "stm32h7b0zb.rs")]
+#[cfg_attr(feature = "stm32h7b3ai", path = "stm32h7b3ai.rs")]
+#[cfg_attr(feature = "stm32h7b3ii", path = "stm32h7b3ii.rs")]
+#[cfg_attr(feature = "stm32h7b3li", path = "stm32h7b3li.rs")]
+#[cfg_attr(feature = "stm32h7b3ni", path = "stm32h7b3ni.rs")]
+#[cfg_attr(feature = "stm32h7b3qi", path = "stm32h7b3qi.rs")]
+#[cfg_attr(feature = "stm32h7b3ri", path = "stm32h7b3ri.rs")]
+#[cfg_attr(feature = "stm32h7b3vi", path = "stm32h7b3vi.rs")]
+#[cfg_attr(feature = "stm32h7b3zi", path = "stm32h7b3zi.rs")]
+#[cfg_attr(feature = "stm32l412c8", path = "stm32l412c8.rs")]
+#[cfg_attr(feature = "stm32l412cb", path = "stm32l412cb.rs")]
+#[cfg_attr(feature = "stm32l412k8", path = "stm32l412k8.rs")]
+#[cfg_attr(feature = "stm32l412kb", path = "stm32l412kb.rs")]
+#[cfg_attr(feature = "stm32l412r8", path = "stm32l412r8.rs")]
+#[cfg_attr(feature = "stm32l412rb", path = "stm32l412rb.rs")]
+#[cfg_attr(feature = "stm32l412t8", path = "stm32l412t8.rs")]
+#[cfg_attr(feature = "stm32l412tb", path = "stm32l412tb.rs")]
+#[cfg_attr(feature = "stm32l422cb", path = "stm32l422cb.rs")]
+#[cfg_attr(feature = "stm32l422kb", path = "stm32l422kb.rs")]
+#[cfg_attr(feature = "stm32l422rb", path = "stm32l422rb.rs")]
+#[cfg_attr(feature = "stm32l422tb", path = "stm32l422tb.rs")]
+#[cfg_attr(feature = "stm32l431cb", path = "stm32l431cb.rs")]
+#[cfg_attr(feature = "stm32l431cc", path = "stm32l431cc.rs")]
+#[cfg_attr(feature = "stm32l431kb", path = "stm32l431kb.rs")]
+#[cfg_attr(feature = "stm32l431kc", path = "stm32l431kc.rs")]
+#[cfg_attr(feature = "stm32l431rb", path = "stm32l431rb.rs")]
+#[cfg_attr(feature = "stm32l431rc", path = "stm32l431rc.rs")]
+#[cfg_attr(feature = "stm32l431vc", path = "stm32l431vc.rs")]
+#[cfg_attr(feature = "stm32l432kb", path = "stm32l432kb.rs")]
+#[cfg_attr(feature = "stm32l432kc", path = "stm32l432kc.rs")]
+#[cfg_attr(feature = "stm32l433cb", path = "stm32l433cb.rs")]
+#[cfg_attr(feature = "stm32l433cc", path = "stm32l433cc.rs")]
+#[cfg_attr(feature = "stm32l433rb", path = "stm32l433rb.rs")]
+#[cfg_attr(feature = "stm32l433rc", path = "stm32l433rc.rs")]
+#[cfg_attr(feature = "stm32l433vc", path = "stm32l433vc.rs")]
+#[cfg_attr(feature = "stm32l442kc", path = "stm32l442kc.rs")]
+#[cfg_attr(feature = "stm32l443cc", path = "stm32l443cc.rs")]
+#[cfg_attr(feature = "stm32l443rc", path = "stm32l443rc.rs")]
+#[cfg_attr(feature = "stm32l443vc", path = "stm32l443vc.rs")]
+#[cfg_attr(feature = "stm32l451cc", path = "stm32l451cc.rs")]
+#[cfg_attr(feature = "stm32l451ce", path = "stm32l451ce.rs")]
+#[cfg_attr(feature = "stm32l451rc", path = "stm32l451rc.rs")]
+#[cfg_attr(feature = "stm32l451re", path = "stm32l451re.rs")]
+#[cfg_attr(feature = "stm32l451vc", path = "stm32l451vc.rs")]
+#[cfg_attr(feature = "stm32l451ve", path = "stm32l451ve.rs")]
+#[cfg_attr(feature = "stm32l452cc", path = "stm32l452cc.rs")]
+#[cfg_attr(feature = "stm32l452ce", path = "stm32l452ce.rs")]
+#[cfg_attr(feature = "stm32l452rc", path = "stm32l452rc.rs")]
+#[cfg_attr(feature = "stm32l452re", path = "stm32l452re.rs")]
+#[cfg_attr(feature = "stm32l452vc", path = "stm32l452vc.rs")]
+#[cfg_attr(feature = "stm32l452ve", path = "stm32l452ve.rs")]
+#[cfg_attr(feature = "stm32l462ce", path = "stm32l462ce.rs")]
+#[cfg_attr(feature = "stm32l462re", path = "stm32l462re.rs")]
+#[cfg_attr(feature = "stm32l462ve", path = "stm32l462ve.rs")]
+#[cfg_attr(feature = "stm32l471qe", path = "stm32l471qe.rs")]
+#[cfg_attr(feature = "stm32l471qg", path = "stm32l471qg.rs")]
+#[cfg_attr(feature = "stm32l471re", path = "stm32l471re.rs")]
+#[cfg_attr(feature = "stm32l471rg", path = "stm32l471rg.rs")]
+#[cfg_attr(feature = "stm32l471ve", path = "stm32l471ve.rs")]
+#[cfg_attr(feature = "stm32l471vg", path = "stm32l471vg.rs")]
+#[cfg_attr(feature = "stm32l471ze", path = "stm32l471ze.rs")]
+#[cfg_attr(feature = "stm32l471zg", path = "stm32l471zg.rs")]
+#[cfg_attr(feature = "stm32l475rc", path = "stm32l475rc.rs")]
+#[cfg_attr(feature = "stm32l475re", path = "stm32l475re.rs")]
+#[cfg_attr(feature = "stm32l475rg", path = "stm32l475rg.rs")]
+#[cfg_attr(feature = "stm32l475vc", path = "stm32l475vc.rs")]
+#[cfg_attr(feature = "stm32l475ve", path = "stm32l475ve.rs")]
+#[cfg_attr(feature = "stm32l475vg", path = "stm32l475vg.rs")]
+#[cfg_attr(feature = "stm32l476je", path = "stm32l476je.rs")]
+#[cfg_attr(feature = "stm32l476jg", path = "stm32l476jg.rs")]
+#[cfg_attr(feature = "stm32l476me", path = "stm32l476me.rs")]
+#[cfg_attr(feature = "stm32l476mg", path = "stm32l476mg.rs")]
+#[cfg_attr(feature = "stm32l476qe", path = "stm32l476qe.rs")]
+#[cfg_attr(feature = "stm32l476qg", path = "stm32l476qg.rs")]
+#[cfg_attr(feature = "stm32l476rc", path = "stm32l476rc.rs")]
+#[cfg_attr(feature = "stm32l476re", path = "stm32l476re.rs")]
+#[cfg_attr(feature = "stm32l476rg", path = "stm32l476rg.rs")]
+#[cfg_attr(feature = "stm32l476vc", path = "stm32l476vc.rs")]
+#[cfg_attr(feature = "stm32l476ve", path = "stm32l476ve.rs")]
+#[cfg_attr(feature = "stm32l476vg", path = "stm32l476vg.rs")]
+#[cfg_attr(feature = "stm32l476ze", path = "stm32l476ze.rs")]
+#[cfg_attr(feature = "stm32l476zg", path = "stm32l476zg.rs")]
+#[cfg_attr(feature = "stm32l485jc", path = "stm32l485jc.rs")]
+#[cfg_attr(feature = "stm32l485je", path = "stm32l485je.rs")]
+#[cfg_attr(feature = "stm32l486jg", path = "stm32l486jg.rs")]
+#[cfg_attr(feature = "stm32l486qg", path = "stm32l486qg.rs")]
+#[cfg_attr(feature = "stm32l486rg", path = "stm32l486rg.rs")]
+#[cfg_attr(feature = "stm32l486vg", path = "stm32l486vg.rs")]
+#[cfg_attr(feature = "stm32l486zg", path = "stm32l486zg.rs")]
+#[cfg_attr(feature = "stm32l496ae", path = "stm32l496ae.rs")]
+#[cfg_attr(feature = "stm32l496ag", path = "stm32l496ag.rs")]
+#[cfg_attr(feature = "stm32l496qe", path = "stm32l496qe.rs")]
+#[cfg_attr(feature = "stm32l496qg", path = "stm32l496qg.rs")]
+#[cfg_attr(feature = "stm32l496re", path = "stm32l496re.rs")]
+#[cfg_attr(feature = "stm32l496rg", path = "stm32l496rg.rs")]
+#[cfg_attr(feature = "stm32l496ve", path = "stm32l496ve.rs")]
+#[cfg_attr(feature = "stm32l496vg", path = "stm32l496vg.rs")]
+#[cfg_attr(feature = "stm32l496wg", path = "stm32l496wg.rs")]
+#[cfg_attr(feature = "stm32l496ze", path = "stm32l496ze.rs")]
+#[cfg_attr(feature = "stm32l496zg", path = "stm32l496zg.rs")]
+#[cfg_attr(feature = "stm32l4a6ag", path = "stm32l4a6ag.rs")]
+#[cfg_attr(feature = "stm32l4a6qg", path = "stm32l4a6qg.rs")]
+#[cfg_attr(feature = "stm32l4a6rg", path = "stm32l4a6rg.rs")]
+#[cfg_attr(feature = "stm32l4a6vg", path = "stm32l4a6vg.rs")]
+#[cfg_attr(feature = "stm32l4a6zg", path = "stm32l4a6zg.rs")]
+#[cfg_attr(feature = "stm32l4p5ae", path = "stm32l4p5ae.rs")]
+#[cfg_attr(feature = "stm32l4p5ag", path = "stm32l4p5ag.rs")]
+#[cfg_attr(feature = "stm32l4p5ce", path = "stm32l4p5ce.rs")]
+#[cfg_attr(feature = "stm32l4p5cg", path = "stm32l4p5cg.rs")]
+#[cfg_attr(feature = "stm32l4p5qe", path = "stm32l4p5qe.rs")]
+#[cfg_attr(feature = "stm32l4p5qg", path = "stm32l4p5qg.rs")]
+#[cfg_attr(feature = "stm32l4p5re", path = "stm32l4p5re.rs")]
+#[cfg_attr(feature = "stm32l4p5rg", path = "stm32l4p5rg.rs")]
+#[cfg_attr(feature = "stm32l4p5ve", path = "stm32l4p5ve.rs")]
+#[cfg_attr(feature = "stm32l4p5vg", path = "stm32l4p5vg.rs")]
+#[cfg_attr(feature = "stm32l4p5ze", path = "stm32l4p5ze.rs")]
+#[cfg_attr(feature = "stm32l4p5zg", path = "stm32l4p5zg.rs")]
+#[cfg_attr(feature = "stm32l4q5ag", path = "stm32l4q5ag.rs")]
+#[cfg_attr(feature = "stm32l4q5cg", path = "stm32l4q5cg.rs")]
+#[cfg_attr(feature = "stm32l4q5qg", path = "stm32l4q5qg.rs")]
+#[cfg_attr(feature = "stm32l4q5rg", path = "stm32l4q5rg.rs")]
+#[cfg_attr(feature = "stm32l4q5vg", path = "stm32l4q5vg.rs")]
+#[cfg_attr(feature = "stm32l4q5zg", path = "stm32l4q5zg.rs")]
+#[cfg_attr(feature = "stm32l4r5ag", path = "stm32l4r5ag.rs")]
+#[cfg_attr(feature = "stm32l4r5ai", path = "stm32l4r5ai.rs")]
+#[cfg_attr(feature = "stm32l4r5qg", path = "stm32l4r5qg.rs")]
+#[cfg_attr(feature = "stm32l4r5qi", path = "stm32l4r5qi.rs")]
+#[cfg_attr(feature = "stm32l4r5vg", path = "stm32l4r5vg.rs")]
+#[cfg_attr(feature = "stm32l4r5vi", path = "stm32l4r5vi.rs")]
+#[cfg_attr(feature = "stm32l4r5zg", path = "stm32l4r5zg.rs")]
+#[cfg_attr(feature = "stm32l4r5zi", path = "stm32l4r5zi.rs")]
+#[cfg_attr(feature = "stm32l4r7ai", path = "stm32l4r7ai.rs")]
+#[cfg_attr(feature = "stm32l4r7vi", path = "stm32l4r7vi.rs")]
+#[cfg_attr(feature = "stm32l4r7zi", path = "stm32l4r7zi.rs")]
+#[cfg_attr(feature = "stm32l4r9ag", path = "stm32l4r9ag.rs")]
+#[cfg_attr(feature = "stm32l4r9ai", path = "stm32l4r9ai.rs")]
+#[cfg_attr(feature = "stm32l4r9vg", path = "stm32l4r9vg.rs")]
+#[cfg_attr(feature = "stm32l4r9vi", path = "stm32l4r9vi.rs")]
+#[cfg_attr(feature = "stm32l4r9zg", path = "stm32l4r9zg.rs")]
+#[cfg_attr(feature = "stm32l4r9zi", path = "stm32l4r9zi.rs")]
+#[cfg_attr(feature = "stm32l4s5ai", path = "stm32l4s5ai.rs")]
+#[cfg_attr(feature = "stm32l4s5qi", path = "stm32l4s5qi.rs")]
+#[cfg_attr(feature = "stm32l4s5vi", path = "stm32l4s5vi.rs")]
+#[cfg_attr(feature = "stm32l4s5zi", path = "stm32l4s5zi.rs")]
+#[cfg_attr(feature = "stm32l4s7ai", path = "stm32l4s7ai.rs")]
+#[cfg_attr(feature = "stm32l4s7vi", path = "stm32l4s7vi.rs")]
+#[cfg_attr(feature = "stm32l4s7zi", path = "stm32l4s7zi.rs")]
+#[cfg_attr(feature = "stm32l4s9ai", path = "stm32l4s9ai.rs")]
+#[cfg_attr(feature = "stm32l4s9vi", path = "stm32l4s9vi.rs")]
+#[cfg_attr(feature = "stm32l4s9zi", path = "stm32l4s9zi.rs")]
+mod chip;
+pub use chip::*;

embassy-stm32/src/pac/stm32f401cb.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401cc.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401cd.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401ce.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401rb.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401rc.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401rd.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401re.rs

@@ -0,0 +1,532 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401vb.rs

@@ -0,0 +1,540 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401vc.rs

@@ -0,0 +1,540 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401vd.rs

@@ -0,0 +1,540 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f401ve.rs

@@ -0,0 +1,540 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 85] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+    ];
+}

embassy-stm32/src/pac/stm32f405oe.rs

@@ -0,0 +1,685 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f405og.rs

@@ -0,0 +1,685 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f405rg.rs

@@ -0,0 +1,685 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f405vg.rs

@@ -0,0 +1,685 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f405zg.rs

@@ -0,0 +1,685 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407ie.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407ig.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407ve.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407vg.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407ze.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f407zg.rs

@@ -0,0 +1,694 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f410c8.rs

@@ -0,0 +1,470 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f410cb.rs

@@ -0,0 +1,470 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f410r8.rs

@@ -0,0 +1,470 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f410rb.rs

@@ -0,0 +1,470 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn SPI2();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f410t8.rs

@@ -0,0 +1,454 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f410tb.rs

@@ -0,0 +1,454 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x40080000 as _);
+impl_rng!(RNG, RNG);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SYSCFG, USART1, USART2
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        LPTIM1 = 97,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SPI1 = 35,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP = 25,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        USART1 = 37,
+        USART2 = 38,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(LPTIM1);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SPI1);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn LPTIM1();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SPI1();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn USART1();
+        fn USART2();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 98] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector { _handler: TIM1_UP },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _reserved: 0 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+    ];
+}

embassy-stm32/src/pac/stm32f411cc.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f411ce.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f411rc.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f411re.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f411vc.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f411ve.rs

@@ -0,0 +1,564 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9,
+    PH10, PH11, PH12, PH13, PH14, PH15, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        USART1 = 37,
+        USART2 = 38,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn USART1();
+        fn USART2();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 86] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+    ];
+}

embassy-stm32/src/pac/stm32f412ce.rs

@@ -0,0 +1,608 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412cg.rs

@@ -0,0 +1,608 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PH0, PH1, PH2, PH3, PH4, PH5,
+    PH6, PH7, PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5,
+    SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412re.rs

@@ -0,0 +1,641 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
+    PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
+    USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412rg.rs

@@ -0,0 +1,641 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7,
+    PH8, PH9, PH10, PH11, PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG,
+    USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412ve.rs

@@ -0,0 +1,714 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412vg.rs

@@ -0,0 +1,714 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412ze.rs

@@ -0,0 +1,714 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f412zg.rs

@@ -0,0 +1,714 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6 = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 97] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: TIM6 },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413cg.rs

@@ -0,0 +1,761 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413ch.rs

@@ -0,0 +1,761 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413mg.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413mh.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413rg.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413rh.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413vg.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413vh.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413zg.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f413zh.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f415og.rs

@@ -0,0 +1,688 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f415rg.rs

@@ -0,0 +1,688 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f415vg.rs

@@ -0,0 +1,688 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f415zg.rs

@@ -0,0 +1,688 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _reserved: 0 },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417ie.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417ig.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417ve.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417vg.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417ze.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f417zg.rs

@@ -0,0 +1,697 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, RNG, SPI1, SPI2, SPI3, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CRYP = 79,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FPU = 81,
+        FSMC = 48,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CRYP);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FPU);
+    declare!(FSMC);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CRYP();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FPU();
+        fn FSMC();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 82] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FSMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _handler: CRYP },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+    ];
+}

embassy-stm32/src/pac/stm32f423ch.rs

@@ -0,0 +1,764 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f423mh.rs

@@ -0,0 +1,781 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f423rh.rs

@@ -0,0 +1,781 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f423vh.rs

@@ -0,0 +1,781 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f423zh.rs

@@ -0,0 +1,781 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, MosiPin, PA10, 5);
+impl_spi_pin!(SPI2, MisoPin, PA12, 5);
+impl_spi_pin!(SPI2, SckPin, PA9, 5);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PC7, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB12, 7);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, MosiPin, PA1, 5);
+impl_spi_pin!(SPI4, MisoPin, PA11, 6);
+impl_spi_pin!(SPI4, SckPin, PB13, 6);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PA10, 6);
+impl_spi_pin!(SPI5, MisoPin, PA12, 6);
+impl_spi_pin!(SPI5, SckPin, PB0, 6);
+impl_spi_pin!(SPI5, MosiPin, PB8, 6);
+impl_spi_pin!(SPI5, SckPin, PE12, 6);
+impl_spi_pin!(SPI5, MisoPin, PE13, 6);
+impl_spi_pin!(SPI5, MosiPin, PE14, 6);
+impl_spi_pin!(SPI5, SckPin, PE2, 6);
+impl_spi_pin!(SPI5, MisoPin, PE5, 6);
+impl_spi_pin!(SPI5, MosiPin, PE6, 6);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, TxPin, PA15, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, RxPin, PB3, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 8);
+impl_usart_pin!(USART3, CtsPin, PB13, 8);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, RxPin, PC5, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PA11, 8);
+impl_usart_pin!(USART6, RxPin, PA12, 8);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3,
+    USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        AES = 79,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        CAN3_RX0 = 75,
+        CAN3_RX1 = 76,
+        CAN3_SCE = 77,
+        CAN3_TX = 74,
+        DFSDM1_FLT0 = 61,
+        DFSDM1_FLT1 = 62,
+        DFSDM2_FLT0 = 98,
+        DFSDM2_FLT1 = 99,
+        DFSDM2_FLT2 = 100,
+        DFSDM2_FLT3 = 101,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMPI2C1_ER = 96,
+        FMPI2C1_EV = 95,
+        FPU = 81,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LPTIM1 = 97,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        PVD = 1,
+        QUADSPI = 92,
+        RCC = 5,
+        RNG = 80,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART10 = 89,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        UART9 = 88,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(AES);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(CAN3_RX0);
+    declare!(CAN3_RX1);
+    declare!(CAN3_SCE);
+    declare!(CAN3_TX);
+    declare!(DFSDM1_FLT0);
+    declare!(DFSDM1_FLT1);
+    declare!(DFSDM2_FLT0);
+    declare!(DFSDM2_FLT1);
+    declare!(DFSDM2_FLT2);
+    declare!(DFSDM2_FLT3);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMPI2C1_ER);
+    declare!(FMPI2C1_EV);
+    declare!(FPU);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LPTIM1);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(PVD);
+    declare!(QUADSPI);
+    declare!(RCC);
+    declare!(RNG);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART10);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(UART9);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn AES();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn CAN3_RX0();
+        fn CAN3_RX1();
+        fn CAN3_SCE();
+        fn CAN3_TX();
+        fn DFSDM1_FLT0();
+        fn DFSDM1_FLT1();
+        fn DFSDM2_FLT0();
+        fn DFSDM2_FLT1();
+        fn DFSDM2_FLT2();
+        fn DFSDM2_FLT3();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMPI2C1_ER();
+        fn FMPI2C1_EV();
+        fn FPU();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LPTIM1();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn PVD();
+        fn QUADSPI();
+        fn RCC();
+        fn RNG();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART10();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn UART9();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 102] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _reserved: 0 },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector {
+            _handler: DFSDM1_FLT0,
+        },
+        Vector {
+            _handler: DFSDM1_FLT1,
+        },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector { _handler: CAN3_TX },
+        Vector { _handler: CAN3_RX0 },
+        Vector { _handler: CAN3_RX1 },
+        Vector { _handler: CAN3_SCE },
+        Vector { _reserved: 0 },
+        Vector { _handler: AES },
+        Vector { _handler: RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _reserved: 0 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: UART9 },
+        Vector { _handler: UART10 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: QUADSPI },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector {
+            _handler: FMPI2C1_EV,
+        },
+        Vector {
+            _handler: FMPI2C1_ER,
+        },
+        Vector { _handler: LPTIM1 },
+        Vector {
+            _handler: DFSDM2_FLT0,
+        },
+        Vector {
+            _handler: DFSDM2_FLT1,
+        },
+        Vector {
+            _handler: DFSDM2_FLT2,
+        },
+        Vector {
+            _handler: DFSDM2_FLT3,
+        },
+    ];
+}

embassy-stm32/src/pac/stm32f427ag.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427ai.rs

@@ -0,0 +1,778 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427ig.rs

@@ -0,0 +1,783 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _);
+impl_spi!(SPI6, APB2);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427ii.rs

@@ -0,0 +1,783 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _);
+impl_spi!(SPI6, APB2);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427vg.rs

@@ -0,0 +1,770 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427vi.rs

@@ -0,0 +1,770 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427zg.rs

@@ -0,0 +1,783 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _);
+impl_spi!(SPI6, APB2);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f427zi.rs

@@ -0,0 +1,783 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SPI6: spi::Spi = spi::Spi(0x40015400 as _);
+impl_spi!(SPI6, APB2);
+impl_spi_pin!(SPI6, MisoPin, PG12, 5);
+impl_spi_pin!(SPI6, SckPin, PG13, 5);
+impl_spi_pin!(SPI6, MosiPin, PG14, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _reserved: 0 },
+        Vector { _reserved: 0 },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f429ag.rs

@@ -0,0 +1,784 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LTDC = 88,
+        LTDC_ER = 89,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: DMA2D },
+    ];
+}

embassy-stm32/src/pac/stm32f429ai.rs

@@ -0,0 +1,784 @@
+#![allow(dead_code)]
+#![allow(unused_imports)]
+#![allow(non_snake_case)]
+
+pub fn GPIO(n: usize) -> gpio::Gpio {
+    gpio::Gpio((0x40020000 + 0x400 * n) as _)
+}
+pub const DMA1: dma::Dma = dma::Dma(0x40026000 as _);
+impl_dma_channel!(DMA1_CH0, 0, 0);
+impl_dma_channel!(DMA1_CH1, 0, 1);
+impl_dma_channel!(DMA1_CH2, 0, 2);
+impl_dma_channel!(DMA1_CH3, 0, 3);
+impl_dma_channel!(DMA1_CH4, 0, 4);
+impl_dma_channel!(DMA1_CH5, 0, 5);
+impl_dma_channel!(DMA1_CH6, 0, 6);
+impl_dma_channel!(DMA1_CH7, 0, 7);
+pub const DMA2: dma::Dma = dma::Dma(0x40026400 as _);
+impl_dma_channel!(DMA2_CH0, 1, 0);
+impl_dma_channel!(DMA2_CH1, 1, 1);
+impl_dma_channel!(DMA2_CH2, 1, 2);
+impl_dma_channel!(DMA2_CH3, 1, 3);
+impl_dma_channel!(DMA2_CH4, 1, 4);
+impl_dma_channel!(DMA2_CH5, 1, 5);
+impl_dma_channel!(DMA2_CH6, 1, 6);
+impl_dma_channel!(DMA2_CH7, 1, 7);
+pub const EXTI: exti::Exti = exti::Exti(0x40013c00 as _);
+pub const GPIOA: gpio::Gpio = gpio::Gpio(0x40020000 as _);
+impl_gpio_pin!(PA0, 0, 0, EXTI0);
+impl_gpio_pin!(PA1, 0, 1, EXTI1);
+impl_gpio_pin!(PA2, 0, 2, EXTI2);
+impl_gpio_pin!(PA3, 0, 3, EXTI3);
+impl_gpio_pin!(PA4, 0, 4, EXTI4);
+impl_gpio_pin!(PA5, 0, 5, EXTI5);
+impl_gpio_pin!(PA6, 0, 6, EXTI6);
+impl_gpio_pin!(PA7, 0, 7, EXTI7);
+impl_gpio_pin!(PA8, 0, 8, EXTI8);
+impl_gpio_pin!(PA9, 0, 9, EXTI9);
+impl_gpio_pin!(PA10, 0, 10, EXTI10);
+impl_gpio_pin!(PA11, 0, 11, EXTI11);
+impl_gpio_pin!(PA12, 0, 12, EXTI12);
+impl_gpio_pin!(PA13, 0, 13, EXTI13);
+impl_gpio_pin!(PA14, 0, 14, EXTI14);
+impl_gpio_pin!(PA15, 0, 15, EXTI15);
+pub const GPIOB: gpio::Gpio = gpio::Gpio(0x40020400 as _);
+impl_gpio_pin!(PB0, 1, 0, EXTI0);
+impl_gpio_pin!(PB1, 1, 1, EXTI1);
+impl_gpio_pin!(PB2, 1, 2, EXTI2);
+impl_gpio_pin!(PB3, 1, 3, EXTI3);
+impl_gpio_pin!(PB4, 1, 4, EXTI4);
+impl_gpio_pin!(PB5, 1, 5, EXTI5);
+impl_gpio_pin!(PB6, 1, 6, EXTI6);
+impl_gpio_pin!(PB7, 1, 7, EXTI7);
+impl_gpio_pin!(PB8, 1, 8, EXTI8);
+impl_gpio_pin!(PB9, 1, 9, EXTI9);
+impl_gpio_pin!(PB10, 1, 10, EXTI10);
+impl_gpio_pin!(PB11, 1, 11, EXTI11);
+impl_gpio_pin!(PB12, 1, 12, EXTI12);
+impl_gpio_pin!(PB13, 1, 13, EXTI13);
+impl_gpio_pin!(PB14, 1, 14, EXTI14);
+impl_gpio_pin!(PB15, 1, 15, EXTI15);
+pub const GPIOC: gpio::Gpio = gpio::Gpio(0x40020800 as _);
+impl_gpio_pin!(PC0, 2, 0, EXTI0);
+impl_gpio_pin!(PC1, 2, 1, EXTI1);
+impl_gpio_pin!(PC2, 2, 2, EXTI2);
+impl_gpio_pin!(PC3, 2, 3, EXTI3);
+impl_gpio_pin!(PC4, 2, 4, EXTI4);
+impl_gpio_pin!(PC5, 2, 5, EXTI5);
+impl_gpio_pin!(PC6, 2, 6, EXTI6);
+impl_gpio_pin!(PC7, 2, 7, EXTI7);
+impl_gpio_pin!(PC8, 2, 8, EXTI8);
+impl_gpio_pin!(PC9, 2, 9, EXTI9);
+impl_gpio_pin!(PC10, 2, 10, EXTI10);
+impl_gpio_pin!(PC11, 2, 11, EXTI11);
+impl_gpio_pin!(PC12, 2, 12, EXTI12);
+impl_gpio_pin!(PC13, 2, 13, EXTI13);
+impl_gpio_pin!(PC14, 2, 14, EXTI14);
+impl_gpio_pin!(PC15, 2, 15, EXTI15);
+pub const GPIOD: gpio::Gpio = gpio::Gpio(0x40020c00 as _);
+impl_gpio_pin!(PD0, 3, 0, EXTI0);
+impl_gpio_pin!(PD1, 3, 1, EXTI1);
+impl_gpio_pin!(PD2, 3, 2, EXTI2);
+impl_gpio_pin!(PD3, 3, 3, EXTI3);
+impl_gpio_pin!(PD4, 3, 4, EXTI4);
+impl_gpio_pin!(PD5, 3, 5, EXTI5);
+impl_gpio_pin!(PD6, 3, 6, EXTI6);
+impl_gpio_pin!(PD7, 3, 7, EXTI7);
+impl_gpio_pin!(PD8, 3, 8, EXTI8);
+impl_gpio_pin!(PD9, 3, 9, EXTI9);
+impl_gpio_pin!(PD10, 3, 10, EXTI10);
+impl_gpio_pin!(PD11, 3, 11, EXTI11);
+impl_gpio_pin!(PD12, 3, 12, EXTI12);
+impl_gpio_pin!(PD13, 3, 13, EXTI13);
+impl_gpio_pin!(PD14, 3, 14, EXTI14);
+impl_gpio_pin!(PD15, 3, 15, EXTI15);
+pub const GPIOE: gpio::Gpio = gpio::Gpio(0x40021000 as _);
+impl_gpio_pin!(PE0, 4, 0, EXTI0);
+impl_gpio_pin!(PE1, 4, 1, EXTI1);
+impl_gpio_pin!(PE2, 4, 2, EXTI2);
+impl_gpio_pin!(PE3, 4, 3, EXTI3);
+impl_gpio_pin!(PE4, 4, 4, EXTI4);
+impl_gpio_pin!(PE5, 4, 5, EXTI5);
+impl_gpio_pin!(PE6, 4, 6, EXTI6);
+impl_gpio_pin!(PE7, 4, 7, EXTI7);
+impl_gpio_pin!(PE8, 4, 8, EXTI8);
+impl_gpio_pin!(PE9, 4, 9, EXTI9);
+impl_gpio_pin!(PE10, 4, 10, EXTI10);
+impl_gpio_pin!(PE11, 4, 11, EXTI11);
+impl_gpio_pin!(PE12, 4, 12, EXTI12);
+impl_gpio_pin!(PE13, 4, 13, EXTI13);
+impl_gpio_pin!(PE14, 4, 14, EXTI14);
+impl_gpio_pin!(PE15, 4, 15, EXTI15);
+pub const GPIOF: gpio::Gpio = gpio::Gpio(0x40021400 as _);
+impl_gpio_pin!(PF0, 5, 0, EXTI0);
+impl_gpio_pin!(PF1, 5, 1, EXTI1);
+impl_gpio_pin!(PF2, 5, 2, EXTI2);
+impl_gpio_pin!(PF3, 5, 3, EXTI3);
+impl_gpio_pin!(PF4, 5, 4, EXTI4);
+impl_gpio_pin!(PF5, 5, 5, EXTI5);
+impl_gpio_pin!(PF6, 5, 6, EXTI6);
+impl_gpio_pin!(PF7, 5, 7, EXTI7);
+impl_gpio_pin!(PF8, 5, 8, EXTI8);
+impl_gpio_pin!(PF9, 5, 9, EXTI9);
+impl_gpio_pin!(PF10, 5, 10, EXTI10);
+impl_gpio_pin!(PF11, 5, 11, EXTI11);
+impl_gpio_pin!(PF12, 5, 12, EXTI12);
+impl_gpio_pin!(PF13, 5, 13, EXTI13);
+impl_gpio_pin!(PF14, 5, 14, EXTI14);
+impl_gpio_pin!(PF15, 5, 15, EXTI15);
+pub const GPIOG: gpio::Gpio = gpio::Gpio(0x40021800 as _);
+impl_gpio_pin!(PG0, 6, 0, EXTI0);
+impl_gpio_pin!(PG1, 6, 1, EXTI1);
+impl_gpio_pin!(PG2, 6, 2, EXTI2);
+impl_gpio_pin!(PG3, 6, 3, EXTI3);
+impl_gpio_pin!(PG4, 6, 4, EXTI4);
+impl_gpio_pin!(PG5, 6, 5, EXTI5);
+impl_gpio_pin!(PG6, 6, 6, EXTI6);
+impl_gpio_pin!(PG7, 6, 7, EXTI7);
+impl_gpio_pin!(PG8, 6, 8, EXTI8);
+impl_gpio_pin!(PG9, 6, 9, EXTI9);
+impl_gpio_pin!(PG10, 6, 10, EXTI10);
+impl_gpio_pin!(PG11, 6, 11, EXTI11);
+impl_gpio_pin!(PG12, 6, 12, EXTI12);
+impl_gpio_pin!(PG13, 6, 13, EXTI13);
+impl_gpio_pin!(PG14, 6, 14, EXTI14);
+impl_gpio_pin!(PG15, 6, 15, EXTI15);
+pub const GPIOH: gpio::Gpio = gpio::Gpio(0x40021c00 as _);
+impl_gpio_pin!(PH0, 7, 0, EXTI0);
+impl_gpio_pin!(PH1, 7, 1, EXTI1);
+impl_gpio_pin!(PH2, 7, 2, EXTI2);
+impl_gpio_pin!(PH3, 7, 3, EXTI3);
+impl_gpio_pin!(PH4, 7, 4, EXTI4);
+impl_gpio_pin!(PH5, 7, 5, EXTI5);
+impl_gpio_pin!(PH6, 7, 6, EXTI6);
+impl_gpio_pin!(PH7, 7, 7, EXTI7);
+impl_gpio_pin!(PH8, 7, 8, EXTI8);
+impl_gpio_pin!(PH9, 7, 9, EXTI9);
+impl_gpio_pin!(PH10, 7, 10, EXTI10);
+impl_gpio_pin!(PH11, 7, 11, EXTI11);
+impl_gpio_pin!(PH12, 7, 12, EXTI12);
+impl_gpio_pin!(PH13, 7, 13, EXTI13);
+impl_gpio_pin!(PH14, 7, 14, EXTI14);
+impl_gpio_pin!(PH15, 7, 15, EXTI15);
+pub const GPIOI: gpio::Gpio = gpio::Gpio(0x40022000 as _);
+impl_gpio_pin!(PI0, 8, 0, EXTI0);
+impl_gpio_pin!(PI1, 8, 1, EXTI1);
+impl_gpio_pin!(PI2, 8, 2, EXTI2);
+impl_gpio_pin!(PI3, 8, 3, EXTI3);
+impl_gpio_pin!(PI4, 8, 4, EXTI4);
+impl_gpio_pin!(PI5, 8, 5, EXTI5);
+impl_gpio_pin!(PI6, 8, 6, EXTI6);
+impl_gpio_pin!(PI7, 8, 7, EXTI7);
+impl_gpio_pin!(PI8, 8, 8, EXTI8);
+impl_gpio_pin!(PI9, 8, 9, EXTI9);
+impl_gpio_pin!(PI10, 8, 10, EXTI10);
+impl_gpio_pin!(PI11, 8, 11, EXTI11);
+impl_gpio_pin!(PI12, 8, 12, EXTI12);
+impl_gpio_pin!(PI13, 8, 13, EXTI13);
+impl_gpio_pin!(PI14, 8, 14, EXTI14);
+impl_gpio_pin!(PI15, 8, 15, EXTI15);
+pub const GPIOJ: gpio::Gpio = gpio::Gpio(0x40022400 as _);
+impl_gpio_pin!(PJ0, 9, 0, EXTI0);
+impl_gpio_pin!(PJ1, 9, 1, EXTI1);
+impl_gpio_pin!(PJ2, 9, 2, EXTI2);
+impl_gpio_pin!(PJ3, 9, 3, EXTI3);
+impl_gpio_pin!(PJ4, 9, 4, EXTI4);
+impl_gpio_pin!(PJ5, 9, 5, EXTI5);
+impl_gpio_pin!(PJ6, 9, 6, EXTI6);
+impl_gpio_pin!(PJ7, 9, 7, EXTI7);
+impl_gpio_pin!(PJ8, 9, 8, EXTI8);
+impl_gpio_pin!(PJ9, 9, 9, EXTI9);
+impl_gpio_pin!(PJ10, 9, 10, EXTI10);
+impl_gpio_pin!(PJ11, 9, 11, EXTI11);
+impl_gpio_pin!(PJ12, 9, 12, EXTI12);
+impl_gpio_pin!(PJ13, 9, 13, EXTI13);
+impl_gpio_pin!(PJ14, 9, 14, EXTI14);
+impl_gpio_pin!(PJ15, 9, 15, EXTI15);
+pub const GPIOK: gpio::Gpio = gpio::Gpio(0x40022800 as _);
+impl_gpio_pin!(PK0, 10, 0, EXTI0);
+impl_gpio_pin!(PK1, 10, 1, EXTI1);
+impl_gpio_pin!(PK2, 10, 2, EXTI2);
+impl_gpio_pin!(PK3, 10, 3, EXTI3);
+impl_gpio_pin!(PK4, 10, 4, EXTI4);
+impl_gpio_pin!(PK5, 10, 5, EXTI5);
+impl_gpio_pin!(PK6, 10, 6, EXTI6);
+impl_gpio_pin!(PK7, 10, 7, EXTI7);
+impl_gpio_pin!(PK8, 10, 8, EXTI8);
+impl_gpio_pin!(PK9, 10, 9, EXTI9);
+impl_gpio_pin!(PK10, 10, 10, EXTI10);
+impl_gpio_pin!(PK11, 10, 11, EXTI11);
+impl_gpio_pin!(PK12, 10, 12, EXTI12);
+impl_gpio_pin!(PK13, 10, 13, EXTI13);
+impl_gpio_pin!(PK14, 10, 14, EXTI14);
+impl_gpio_pin!(PK15, 10, 15, EXTI15);
+pub const RNG: rng::Rng = rng::Rng(0x50060800 as _);
+impl_rng!(RNG, HASH_RNG);
+pub const SPI1: spi::Spi = spi::Spi(0x40013000 as _);
+impl_spi!(SPI1, APB2);
+impl_spi_pin!(SPI1, SckPin, PA5, 5);
+impl_spi_pin!(SPI1, MisoPin, PA6, 5);
+impl_spi_pin!(SPI1, MosiPin, PA7, 5);
+impl_spi_pin!(SPI1, SckPin, PB3, 5);
+impl_spi_pin!(SPI1, MisoPin, PB4, 5);
+impl_spi_pin!(SPI1, MosiPin, PB5, 5);
+pub const SPI2: spi::Spi = spi::Spi(0x40003800 as _);
+impl_spi!(SPI2, APB1);
+impl_spi_pin!(SPI2, SckPin, PB10, 5);
+impl_spi_pin!(SPI2, SckPin, PB13, 5);
+impl_spi_pin!(SPI2, MisoPin, PB14, 5);
+impl_spi_pin!(SPI2, MosiPin, PB15, 5);
+impl_spi_pin!(SPI2, MisoPin, PC2, 5);
+impl_spi_pin!(SPI2, MosiPin, PC3, 5);
+impl_spi_pin!(SPI2, SckPin, PD3, 5);
+impl_spi_pin!(SPI2, SckPin, PI1, 5);
+impl_spi_pin!(SPI2, MisoPin, PI2, 5);
+impl_spi_pin!(SPI2, MosiPin, PI3, 5);
+pub const SPI3: spi::Spi = spi::Spi(0x40003c00 as _);
+impl_spi!(SPI3, APB1);
+impl_spi_pin!(SPI3, SckPin, PB3, 6);
+impl_spi_pin!(SPI3, MisoPin, PB4, 6);
+impl_spi_pin!(SPI3, MosiPin, PB5, 6);
+impl_spi_pin!(SPI3, SckPin, PC10, 6);
+impl_spi_pin!(SPI3, MisoPin, PC11, 6);
+impl_spi_pin!(SPI3, MosiPin, PC12, 6);
+impl_spi_pin!(SPI3, MosiPin, PD6, 5);
+pub const SPI4: spi::Spi = spi::Spi(0x40013400 as _);
+impl_spi!(SPI4, APB2);
+impl_spi_pin!(SPI4, SckPin, PE12, 5);
+impl_spi_pin!(SPI4, MisoPin, PE13, 5);
+impl_spi_pin!(SPI4, MosiPin, PE14, 5);
+impl_spi_pin!(SPI4, SckPin, PE2, 5);
+impl_spi_pin!(SPI4, MisoPin, PE5, 5);
+impl_spi_pin!(SPI4, MosiPin, PE6, 5);
+pub const SPI5: spi::Spi = spi::Spi(0x40015000 as _);
+impl_spi!(SPI5, APB2);
+impl_spi_pin!(SPI5, MosiPin, PF11, 5);
+impl_spi_pin!(SPI5, SckPin, PF7, 5);
+impl_spi_pin!(SPI5, MisoPin, PF8, 5);
+impl_spi_pin!(SPI5, MosiPin, PF9, 5);
+impl_spi_pin!(SPI5, SckPin, PH6, 5);
+impl_spi_pin!(SPI5, MisoPin, PH7, 5);
+pub const SYSCFG: syscfg::Syscfg = syscfg::Syscfg(0x40013800 as _);
+pub const USART1: usart::Usart = usart::Usart(0x40011000 as _);
+impl_usart!(USART1);
+impl_usart_pin!(USART1, RxPin, PA10, 7);
+impl_usart_pin!(USART1, CtsPin, PA11, 7);
+impl_usart_pin!(USART1, RtsPin, PA12, 7);
+impl_usart_pin!(USART1, CkPin, PA8, 7);
+impl_usart_pin!(USART1, TxPin, PA9, 7);
+impl_usart_pin!(USART1, TxPin, PB6, 7);
+impl_usart_pin!(USART1, RxPin, PB7, 7);
+pub const USART2: usart::Usart = usart::Usart(0x40004400 as _);
+impl_usart!(USART2);
+impl_usart_pin!(USART2, CtsPin, PA0, 7);
+impl_usart_pin!(USART2, RtsPin, PA1, 7);
+impl_usart_pin!(USART2, TxPin, PA2, 7);
+impl_usart_pin!(USART2, RxPin, PA3, 7);
+impl_usart_pin!(USART2, CkPin, PA4, 7);
+impl_usart_pin!(USART2, CtsPin, PD3, 7);
+impl_usart_pin!(USART2, RtsPin, PD4, 7);
+impl_usart_pin!(USART2, TxPin, PD5, 7);
+impl_usart_pin!(USART2, RxPin, PD6, 7);
+impl_usart_pin!(USART2, CkPin, PD7, 7);
+pub const USART3: usart::Usart = usart::Usart(0x40004800 as _);
+impl_usart!(USART3);
+impl_usart_pin!(USART3, TxPin, PB10, 7);
+impl_usart_pin!(USART3, RxPin, PB11, 7);
+impl_usart_pin!(USART3, CkPin, PB12, 7);
+impl_usart_pin!(USART3, CtsPin, PB13, 7);
+impl_usart_pin!(USART3, RtsPin, PB14, 7);
+impl_usart_pin!(USART3, TxPin, PC10, 7);
+impl_usart_pin!(USART3, RxPin, PC11, 7);
+impl_usart_pin!(USART3, CkPin, PC12, 7);
+impl_usart_pin!(USART3, CkPin, PD10, 7);
+impl_usart_pin!(USART3, CtsPin, PD11, 7);
+impl_usart_pin!(USART3, RtsPin, PD12, 7);
+impl_usart_pin!(USART3, TxPin, PD8, 7);
+impl_usart_pin!(USART3, RxPin, PD9, 7);
+pub const USART6: usart::Usart = usart::Usart(0x40011400 as _);
+impl_usart!(USART6);
+impl_usart_pin!(USART6, TxPin, PC6, 8);
+impl_usart_pin!(USART6, RxPin, PC7, 8);
+impl_usart_pin!(USART6, CkPin, PC8, 8);
+impl_usart_pin!(USART6, RtsPin, PG12, 8);
+impl_usart_pin!(USART6, CtsPin, PG13, 8);
+impl_usart_pin!(USART6, TxPin, PG14, 8);
+impl_usart_pin!(USART6, CtsPin, PG15, 8);
+impl_usart_pin!(USART6, CkPin, PG7, 8);
+impl_usart_pin!(USART6, RtsPin, PG8, 8);
+impl_usart_pin!(USART6, RxPin, PG9, 8);
+pub use regs::dma_v2 as dma;
+pub use regs::exti_v1 as exti;
+pub use regs::gpio_v2 as gpio;
+pub use regs::rng_v1 as rng;
+pub use regs::spi_v1 as spi;
+pub use regs::syscfg_f4 as syscfg;
+pub use regs::usart_v1 as usart;
+mod regs;
+use embassy_extras::peripherals;
+pub use regs::generic;
+peripherals!(
+    EXTI0, EXTI1, EXTI2, EXTI3, EXTI4, EXTI5, EXTI6, EXTI7, EXTI8, EXTI9, EXTI10, EXTI11, EXTI12,
+    EXTI13, EXTI14, EXTI15, DMA1_CH0, DMA1_CH1, DMA1_CH2, DMA1_CH3, DMA1_CH4, DMA1_CH5, DMA1_CH6,
+    DMA1_CH7, DMA2_CH0, DMA2_CH1, DMA2_CH2, DMA2_CH3, DMA2_CH4, DMA2_CH5, DMA2_CH6, DMA2_CH7, EXTI,
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15, PB0, PB1,
+    PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15, PC0, PC1, PC2, PC3,
+    PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15, PD0, PD1, PD2, PD3, PD4, PD5,
+    PD6, PD7, PD8, PD9, PD10, PD11, PD12, PD13, PD14, PD15, PE0, PE1, PE2, PE3, PE4, PE5, PE6, PE7,
+    PE8, PE9, PE10, PE11, PE12, PE13, PE14, PE15, PF0, PF1, PF2, PF3, PF4, PF5, PF6, PF7, PF8, PF9,
+    PF10, PF11, PF12, PF13, PF14, PF15, PG0, PG1, PG2, PG3, PG4, PG5, PG6, PG7, PG8, PG9, PG10,
+    PG11, PG12, PG13, PG14, PG15, PH0, PH1, PH2, PH3, PH4, PH5, PH6, PH7, PH8, PH9, PH10, PH11,
+    PH12, PH13, PH14, PH15, PI0, PI1, PI2, PI3, PI4, PI5, PI6, PI7, PI8, PI9, PI10, PI11, PI12,
+    PI13, PI14, PI15, PJ0, PJ1, PJ2, PJ3, PJ4, PJ5, PJ6, PJ7, PJ8, PJ9, PJ10, PJ11, PJ12, PJ13,
+    PJ14, PJ15, PK0, PK1, PK2, PK3, PK4, PK5, PK6, PK7, PK8, PK9, PK10, PK11, PK12, PK13, PK14,
+    PK15, RNG, SPI1, SPI2, SPI3, SPI4, SPI5, SYSCFG, USART1, USART2, USART3, USART6
+);
+
+pub mod interrupt {
+    pub use cortex_m::interrupt::{CriticalSection, Mutex};
+    pub use embassy::interrupt::{declare, take, Interrupt};
+    pub use embassy_extras::interrupt::Priority4 as Priority;
+
+    #[derive(Copy, Clone, Debug, PartialEq, Eq)]
+    #[allow(non_camel_case_types)]
+    pub enum InterruptEnum {
+        ADC = 18,
+        CAN1_RX0 = 20,
+        CAN1_RX1 = 21,
+        CAN1_SCE = 22,
+        CAN1_TX = 19,
+        CAN2_RX0 = 64,
+        CAN2_RX1 = 65,
+        CAN2_SCE = 66,
+        CAN2_TX = 63,
+        DCMI = 78,
+        DMA1_Stream0 = 11,
+        DMA1_Stream1 = 12,
+        DMA1_Stream2 = 13,
+        DMA1_Stream3 = 14,
+        DMA1_Stream4 = 15,
+        DMA1_Stream5 = 16,
+        DMA1_Stream6 = 17,
+        DMA1_Stream7 = 47,
+        DMA2D = 90,
+        DMA2_Stream0 = 56,
+        DMA2_Stream1 = 57,
+        DMA2_Stream2 = 58,
+        DMA2_Stream3 = 59,
+        DMA2_Stream4 = 60,
+        DMA2_Stream5 = 68,
+        DMA2_Stream6 = 69,
+        DMA2_Stream7 = 70,
+        ETH = 61,
+        ETH_WKUP = 62,
+        EXTI0 = 6,
+        EXTI1 = 7,
+        EXTI15_10 = 40,
+        EXTI2 = 8,
+        EXTI3 = 9,
+        EXTI4 = 10,
+        EXTI9_5 = 23,
+        FLASH = 4,
+        FMC = 48,
+        FPU = 81,
+        HASH_RNG = 80,
+        I2C1_ER = 32,
+        I2C1_EV = 31,
+        I2C2_ER = 34,
+        I2C2_EV = 33,
+        I2C3_ER = 73,
+        I2C3_EV = 72,
+        LTDC = 88,
+        LTDC_ER = 89,
+        OTG_FS = 67,
+        OTG_FS_WKUP = 42,
+        OTG_HS = 77,
+        OTG_HS_EP1_IN = 75,
+        OTG_HS_EP1_OUT = 74,
+        OTG_HS_WKUP = 76,
+        PVD = 1,
+        RCC = 5,
+        RTC_Alarm = 41,
+        RTC_WKUP = 3,
+        SAI1 = 87,
+        SDIO = 49,
+        SPI1 = 35,
+        SPI2 = 36,
+        SPI3 = 51,
+        SPI4 = 84,
+        SPI5 = 85,
+        SPI6 = 86,
+        TAMP_STAMP = 2,
+        TIM1_BRK_TIM9 = 24,
+        TIM1_CC = 27,
+        TIM1_TRG_COM_TIM11 = 26,
+        TIM1_UP_TIM10 = 25,
+        TIM2 = 28,
+        TIM3 = 29,
+        TIM4 = 30,
+        TIM5 = 50,
+        TIM6_DAC = 54,
+        TIM7 = 55,
+        TIM8_BRK_TIM12 = 43,
+        TIM8_CC = 46,
+        TIM8_TRG_COM_TIM14 = 45,
+        TIM8_UP_TIM13 = 44,
+        UART4 = 52,
+        UART5 = 53,
+        UART7 = 82,
+        UART8 = 83,
+        USART1 = 37,
+        USART2 = 38,
+        USART3 = 39,
+        USART6 = 71,
+        WWDG = 0,
+    }
+    unsafe impl cortex_m::interrupt::InterruptNumber for InterruptEnum {
+        #[inline(always)]
+        fn number(self) -> u16 {
+            self as u16
+        }
+    }
+
+    declare!(ADC);
+    declare!(CAN1_RX0);
+    declare!(CAN1_RX1);
+    declare!(CAN1_SCE);
+    declare!(CAN1_TX);
+    declare!(CAN2_RX0);
+    declare!(CAN2_RX1);
+    declare!(CAN2_SCE);
+    declare!(CAN2_TX);
+    declare!(DCMI);
+    declare!(DMA1_Stream0);
+    declare!(DMA1_Stream1);
+    declare!(DMA1_Stream2);
+    declare!(DMA1_Stream3);
+    declare!(DMA1_Stream4);
+    declare!(DMA1_Stream5);
+    declare!(DMA1_Stream6);
+    declare!(DMA1_Stream7);
+    declare!(DMA2D);
+    declare!(DMA2_Stream0);
+    declare!(DMA2_Stream1);
+    declare!(DMA2_Stream2);
+    declare!(DMA2_Stream3);
+    declare!(DMA2_Stream4);
+    declare!(DMA2_Stream5);
+    declare!(DMA2_Stream6);
+    declare!(DMA2_Stream7);
+    declare!(ETH);
+    declare!(ETH_WKUP);
+    declare!(EXTI0);
+    declare!(EXTI1);
+    declare!(EXTI15_10);
+    declare!(EXTI2);
+    declare!(EXTI3);
+    declare!(EXTI4);
+    declare!(EXTI9_5);
+    declare!(FLASH);
+    declare!(FMC);
+    declare!(FPU);
+    declare!(HASH_RNG);
+    declare!(I2C1_ER);
+    declare!(I2C1_EV);
+    declare!(I2C2_ER);
+    declare!(I2C2_EV);
+    declare!(I2C3_ER);
+    declare!(I2C3_EV);
+    declare!(LTDC);
+    declare!(LTDC_ER);
+    declare!(OTG_FS);
+    declare!(OTG_FS_WKUP);
+    declare!(OTG_HS);
+    declare!(OTG_HS_EP1_IN);
+    declare!(OTG_HS_EP1_OUT);
+    declare!(OTG_HS_WKUP);
+    declare!(PVD);
+    declare!(RCC);
+    declare!(RTC_Alarm);
+    declare!(RTC_WKUP);
+    declare!(SAI1);
+    declare!(SDIO);
+    declare!(SPI1);
+    declare!(SPI2);
+    declare!(SPI3);
+    declare!(SPI4);
+    declare!(SPI5);
+    declare!(SPI6);
+    declare!(TAMP_STAMP);
+    declare!(TIM1_BRK_TIM9);
+    declare!(TIM1_CC);
+    declare!(TIM1_TRG_COM_TIM11);
+    declare!(TIM1_UP_TIM10);
+    declare!(TIM2);
+    declare!(TIM3);
+    declare!(TIM4);
+    declare!(TIM5);
+    declare!(TIM6_DAC);
+    declare!(TIM7);
+    declare!(TIM8_BRK_TIM12);
+    declare!(TIM8_CC);
+    declare!(TIM8_TRG_COM_TIM14);
+    declare!(TIM8_UP_TIM13);
+    declare!(UART4);
+    declare!(UART5);
+    declare!(UART7);
+    declare!(UART8);
+    declare!(USART1);
+    declare!(USART2);
+    declare!(USART3);
+    declare!(USART6);
+    declare!(WWDG);
+}
+mod interrupt_vector {
+    extern "C" {
+        fn ADC();
+        fn CAN1_RX0();
+        fn CAN1_RX1();
+        fn CAN1_SCE();
+        fn CAN1_TX();
+        fn CAN2_RX0();
+        fn CAN2_RX1();
+        fn CAN2_SCE();
+        fn CAN2_TX();
+        fn DCMI();
+        fn DMA1_Stream0();
+        fn DMA1_Stream1();
+        fn DMA1_Stream2();
+        fn DMA1_Stream3();
+        fn DMA1_Stream4();
+        fn DMA1_Stream5();
+        fn DMA1_Stream6();
+        fn DMA1_Stream7();
+        fn DMA2D();
+        fn DMA2_Stream0();
+        fn DMA2_Stream1();
+        fn DMA2_Stream2();
+        fn DMA2_Stream3();
+        fn DMA2_Stream4();
+        fn DMA2_Stream5();
+        fn DMA2_Stream6();
+        fn DMA2_Stream7();
+        fn ETH();
+        fn ETH_WKUP();
+        fn EXTI0();
+        fn EXTI1();
+        fn EXTI15_10();
+        fn EXTI2();
+        fn EXTI3();
+        fn EXTI4();
+        fn EXTI9_5();
+        fn FLASH();
+        fn FMC();
+        fn FPU();
+        fn HASH_RNG();
+        fn I2C1_ER();
+        fn I2C1_EV();
+        fn I2C2_ER();
+        fn I2C2_EV();
+        fn I2C3_ER();
+        fn I2C3_EV();
+        fn LTDC();
+        fn LTDC_ER();
+        fn OTG_FS();
+        fn OTG_FS_WKUP();
+        fn OTG_HS();
+        fn OTG_HS_EP1_IN();
+        fn OTG_HS_EP1_OUT();
+        fn OTG_HS_WKUP();
+        fn PVD();
+        fn RCC();
+        fn RTC_Alarm();
+        fn RTC_WKUP();
+        fn SAI1();
+        fn SDIO();
+        fn SPI1();
+        fn SPI2();
+        fn SPI3();
+        fn SPI4();
+        fn SPI5();
+        fn SPI6();
+        fn TAMP_STAMP();
+        fn TIM1_BRK_TIM9();
+        fn TIM1_CC();
+        fn TIM1_TRG_COM_TIM11();
+        fn TIM1_UP_TIM10();
+        fn TIM2();
+        fn TIM3();
+        fn TIM4();
+        fn TIM5();
+        fn TIM6_DAC();
+        fn TIM7();
+        fn TIM8_BRK_TIM12();
+        fn TIM8_CC();
+        fn TIM8_TRG_COM_TIM14();
+        fn TIM8_UP_TIM13();
+        fn UART4();
+        fn UART5();
+        fn UART7();
+        fn UART8();
+        fn USART1();
+        fn USART2();
+        fn USART3();
+        fn USART6();
+        fn WWDG();
+    }
+    pub union Vector {
+        _handler: unsafe extern "C" fn(),
+        _reserved: u32,
+    }
+    #[link_section = ".vector_table.interrupts"]
+    #[no_mangle]
+    pub static __INTERRUPTS: [Vector; 91] = [
+        Vector { _handler: WWDG },
+        Vector { _handler: PVD },
+        Vector {
+            _handler: TAMP_STAMP,
+        },
+        Vector { _handler: RTC_WKUP },
+        Vector { _handler: FLASH },
+        Vector { _handler: RCC },
+        Vector { _handler: EXTI0 },
+        Vector { _handler: EXTI1 },
+        Vector { _handler: EXTI2 },
+        Vector { _handler: EXTI3 },
+        Vector { _handler: EXTI4 },
+        Vector {
+            _handler: DMA1_Stream0,
+        },
+        Vector {
+            _handler: DMA1_Stream1,
+        },
+        Vector {
+            _handler: DMA1_Stream2,
+        },
+        Vector {
+            _handler: DMA1_Stream3,
+        },
+        Vector {
+            _handler: DMA1_Stream4,
+        },
+        Vector {
+            _handler: DMA1_Stream5,
+        },
+        Vector {
+            _handler: DMA1_Stream6,
+        },
+        Vector { _handler: ADC },
+        Vector { _handler: CAN1_TX },
+        Vector { _handler: CAN1_RX0 },
+        Vector { _handler: CAN1_RX1 },
+        Vector { _handler: CAN1_SCE },
+        Vector { _handler: EXTI9_5 },
+        Vector {
+            _handler: TIM1_BRK_TIM9,
+        },
+        Vector {
+            _handler: TIM1_UP_TIM10,
+        },
+        Vector {
+            _handler: TIM1_TRG_COM_TIM11,
+        },
+        Vector { _handler: TIM1_CC },
+        Vector { _handler: TIM2 },
+        Vector { _handler: TIM3 },
+        Vector { _handler: TIM4 },
+        Vector { _handler: I2C1_EV },
+        Vector { _handler: I2C1_ER },
+        Vector { _handler: I2C2_EV },
+        Vector { _handler: I2C2_ER },
+        Vector { _handler: SPI1 },
+        Vector { _handler: SPI2 },
+        Vector { _handler: USART1 },
+        Vector { _handler: USART2 },
+        Vector { _handler: USART3 },
+        Vector {
+            _handler: EXTI15_10,
+        },
+        Vector {
+            _handler: RTC_Alarm,
+        },
+        Vector {
+            _handler: OTG_FS_WKUP,
+        },
+        Vector {
+            _handler: TIM8_BRK_TIM12,
+        },
+        Vector {
+            _handler: TIM8_UP_TIM13,
+        },
+        Vector {
+            _handler: TIM8_TRG_COM_TIM14,
+        },
+        Vector { _handler: TIM8_CC },
+        Vector {
+            _handler: DMA1_Stream7,
+        },
+        Vector { _handler: FMC },
+        Vector { _handler: SDIO },
+        Vector { _handler: TIM5 },
+        Vector { _handler: SPI3 },
+        Vector { _handler: UART4 },
+        Vector { _handler: UART5 },
+        Vector { _handler: TIM6_DAC },
+        Vector { _handler: TIM7 },
+        Vector {
+            _handler: DMA2_Stream0,
+        },
+        Vector {
+            _handler: DMA2_Stream1,
+        },
+        Vector {
+            _handler: DMA2_Stream2,
+        },
+        Vector {
+            _handler: DMA2_Stream3,
+        },
+        Vector {
+            _handler: DMA2_Stream4,
+        },
+        Vector { _handler: ETH },
+        Vector { _handler: ETH_WKUP },
+        Vector { _handler: CAN2_TX },
+        Vector { _handler: CAN2_RX0 },
+        Vector { _handler: CAN2_RX1 },
+        Vector { _handler: CAN2_SCE },
+        Vector { _handler: OTG_FS },
+        Vector {
+            _handler: DMA2_Stream5,
+        },
+        Vector {
+            _handler: DMA2_Stream6,
+        },
+        Vector {
+            _handler: DMA2_Stream7,
+        },
+        Vector { _handler: USART6 },
+        Vector { _handler: I2C3_EV },
+        Vector { _handler: I2C3_ER },
+        Vector {
+            _handler: OTG_HS_EP1_OUT,
+        },
+        Vector {
+            _handler: OTG_HS_EP1_IN,
+        },
+        Vector {
+            _handler: OTG_HS_WKUP,
+        },
+        Vector { _handler: OTG_HS },
+        Vector { _handler: DCMI },
+        Vector { _reserved: 0 },
+        Vector { _handler: HASH_RNG },
+        Vector { _handler: FPU },
+        Vector { _handler: UART7 },
+        Vector { _handler: UART8 },
+        Vector { _handler: SPI4 },
+        Vector { _handler: SPI5 },
+        Vector { _handler: SPI6 },
+        Vector { _handler: SAI1 },
+        Vector { _handler: LTDC },
+        Vector { _handler: LTDC_ER },
+        Vector { _handler: DMA2D },
+    ];
+}