wpan: fix ipcc delay
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e7ab044935
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d7ce823d79
@ -93,15 +93,26 @@ pub struct Ipcc;
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impl Ipcc {
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pub fn enable(_config: Config) {
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// TODO: move these lines to the rcc mod
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// set LPTIM1 & LPTIM2 clock source
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crate::pac::RCC.ccipr().modify(|w| {
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w.set_lptim1sel(0b00); // PCLK
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w.set_lptim2sel(0b00); // PCLK
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});
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// set RF wake-up clock = LSE
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crate::pac::RCC.csr().modify(|w| w.set_rfwkpsel(0b01));
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IPCC::enable();
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IPCC::reset();
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// insert bus access and fence for delay
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IPCC::enable();
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compiler_fence(Ordering::SeqCst);
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IPCC::set_cpu2(true);
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_configure_pwr();
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let regs = IPCC::regs();
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regs.cpu(0).cr().modify(|w| {
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IPCC::regs().cpu(0).cr().modify(|w| {
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w.set_rxoie(true);
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w.set_txfie(true);
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});
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@ -263,18 +274,3 @@ pub(crate) mod sealed {
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fn state() -> &'static State;
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}
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}
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fn _configure_pwr() {
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// TODO: move the rest of this to rcc
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let rcc = crate::pac::RCC;
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// TODO: required
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// set RF wake-up clock = LSE
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rcc.csr().modify(|w| w.set_rfwkpsel(0b01));
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// set LPTIM1 & LPTIM2 clock source
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rcc.ccipr().modify(|w| {
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w.set_lptim1sel(0b00); // PCLK
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w.set_lptim2sel(0b00); // PCLK
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});
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}
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@ -143,6 +143,8 @@ impl BackupDomain {
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Self::modify(|w| {});
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trace!("BDCR ok: {:08x}", Self::read().0);
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compiler_fence(Ordering::SeqCst);
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return;
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}
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