stm32/sdmmc: remove cfg_if.
This commit is contained in:
Dario Nieuwenhuis
parent
9202dbf32a
commit
df7ef1d98f
@ -135,57 +135,53 @@ enum Response {
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Long = 3,
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}
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
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/// `sdmmc_ck` in Hertz.
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///
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/// Returns `(bypass, clk_div, clk_f)`, where `bypass` enables clock divisor bypass (only sdmmc_v1),
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/// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
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fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
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// sdmmc_v1 maximum clock is 50 MHz
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if sdmmc_ck > 50_000_000 {
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return Err(Error::BadClock);
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}
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/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
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/// `sdmmc_ck` in Hertz.
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///
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/// Returns `(bypass, clk_div, clk_f)`, where `bypass` enables clock divisor bypass (only sdmmc_v1),
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/// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
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#[cfg(sdmmc_v1)]
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fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u8, Hertz), Error> {
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// sdmmc_v1 maximum clock is 50 MHz
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if sdmmc_ck > 50_000_000 {
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return Err(Error::BadClock);
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}
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// bypass divisor
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if ker_ck.0 <= sdmmc_ck {
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return Ok((true, 0, ker_ck));
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}
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// bypass divisor
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if ker_ck.0 <= sdmmc_ck {
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return Ok((true, 0, ker_ck));
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}
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// `ker_ck / sdmmc_ck` rounded up
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let clk_div = match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
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0 | 1 => Ok(0),
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x @ 2..=258 => {
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Ok((x - 2) as u8)
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}
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_ => Err(Error::BadClock),
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}?;
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// `ker_ck / sdmmc_ck` rounded up
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let clk_div = match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
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0 | 1 => Ok(0),
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x @ 2..=258 => Ok((x - 2) as u8),
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_ => Err(Error::BadClock),
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}?;
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// SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]
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let clk_f = Hertz(ker_ck.0 / (clk_div as u32 + 2));
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Ok((false, clk_div, clk_f))
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}
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} else if #[cfg(sdmmc_v2)] {
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/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
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/// `sdmmc_ck` in Hertz.
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///
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/// Returns `(bypass, clk_div, clk_f)`, where `bypass` enables clock divisor bypass (only sdmmc_v1),
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/// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
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fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u16, Hertz), Error> {
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// `ker_ck / sdmmc_ck` rounded up
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match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
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0 | 1 => Ok((false, 0, ker_ck)),
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x @ 2..=2046 => {
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// SDMMC_CK frequency = SDMMCCLK / [CLKDIV + 2]
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let clk_div = ((x + 1) / 2) as u16;
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let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2));
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Ok((false, clk_div, clk))
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}
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_ => Err(Error::BadClock),
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}
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// SDIO_CK frequency = SDIOCLK / [CLKDIV + 2]
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let clk_f = Hertz(ker_ck.0 / (clk_div as u32 + 2));
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Ok((false, clk_div, clk_f))
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}
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/// Calculate clock divisor. Returns a SDMMC_CK less than or equal to
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/// `sdmmc_ck` in Hertz.
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///
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/// Returns `(bypass, clk_div, clk_f)`, where `bypass` enables clock divisor bypass (only sdmmc_v1),
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/// `clk_div` is the divisor register value and `clk_f` is the resulting new clock frequency.
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#[cfg(sdmmc_v2)]
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fn clk_div(ker_ck: Hertz, sdmmc_ck: u32) -> Result<(bool, u16, Hertz), Error> {
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// `ker_ck / sdmmc_ck` rounded up
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match (ker_ck.0 + sdmmc_ck - 1) / sdmmc_ck {
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0 | 1 => Ok((false, 0, ker_ck)),
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x @ 2..=2046 => {
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// SDMMC_CK frequency = SDMMCCLK / [CLKDIV + 2]
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let clk_div = ((x + 1) / 2) as u16;
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let clk = Hertz(ker_ck.0 / (clk_div as u32 * 2));
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Ok((false, clk_div, clk))
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}
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_ => Err(Error::BadClock),
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}
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}
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@ -904,13 +900,10 @@ impl SdmmcInner {
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// NOTE(unsafe) Atomic read with no side-effects
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unsafe {
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let status = regs.star().read();
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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status.rxact() || status.txact()
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} else if #[cfg(sdmmc_v2)] {
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status.dpsmact()
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}
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}
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#[cfg(sdmmc_v1)]
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return status.rxact() || status.txact();
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#[cfg(sdmmc_v2)]
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return status.dpsmact();
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}
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}
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@ -922,13 +915,10 @@ impl SdmmcInner {
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// NOTE(unsafe) Atomic read with no side-effects
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unsafe {
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let status = regs.star().read();
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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status.cmdact()
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} else if #[cfg(sdmmc_v2)] {
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status.cpsmact()
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}
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}
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#[cfg(sdmmc_v1)]
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return status.cmdact();
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#[cfg(sdmmc_v2)]
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return status.cpsmact();
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}
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}
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@ -961,20 +951,26 @@ impl SdmmcInner {
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regs.dtimer().write(|w| w.set_datatime(data_transfer_timeout));
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regs.dlenr().write(|w| w.set_datalength(length_bytes));
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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let request = dma.request();
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dma.start_read(request, regs.fifor().ptr() as *const u32, buffer, crate::dma::TransferOptions {
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#[cfg(sdmmc_v1)]
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{
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let request = dma.request();
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dma.start_read(
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request,
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regs.fifor().ptr() as *const u32,
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buffer,
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crate::dma::TransferOptions {
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pburst: crate::dma::Burst::Incr4,
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mburst: crate::dma::Burst::Incr4,
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flow_ctrl: crate::dma::FlowControl::Peripheral,
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fifo_threshold: Some(crate::dma::FifoThreshold::Full),
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..Default::default()
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});
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} else if #[cfg(sdmmc_v2)] {
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regs.idmabase0r().write(|w| w.set_idmabase0(buffer as *mut u32 as u32));
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regs.idmactrlr().modify(|w| w.set_idmaen(true));
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}
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},
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);
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}
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#[cfg(sdmmc_v2)]
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{
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regs.idmabase0r().write(|w| w.set_idmabase0(buffer as *mut u32 as u32));
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regs.idmactrlr().modify(|w| w.set_idmaen(true));
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}
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regs.dctrl().modify(|w| {
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@ -1011,20 +1007,27 @@ impl SdmmcInner {
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regs.dtimer().write(|w| w.set_datatime(data_transfer_timeout));
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regs.dlenr().write(|w| w.set_datalength(length_bytes));
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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let request = dma.request();
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dma.start_write(request, buffer, regs.fifor().ptr() as *mut u32, crate::dma::TransferOptions {
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#[cfg(sdmmc_v1)]
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{
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let request = dma.request();
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dma.start_write(
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request,
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buffer,
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regs.fifor().ptr() as *mut u32,
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crate::dma::TransferOptions {
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pburst: crate::dma::Burst::Incr4,
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mburst: crate::dma::Burst::Incr4,
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flow_ctrl: crate::dma::FlowControl::Peripheral,
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fifo_threshold: Some(crate::dma::FifoThreshold::Full),
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..Default::default()
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});
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} else if #[cfg(sdmmc_v2)] {
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regs.idmabase0r().write(|w| w.set_idmabase0(buffer as *const u32 as u32));
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regs.idmactrlr().modify(|w| w.set_idmaen(true));
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}
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},
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);
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}
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#[cfg(sdmmc_v2)]
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{
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regs.idmabase0r()
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.write(|w| w.set_idmabase0(buffer as *const u32 as u32));
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regs.idmactrlr().modify(|w| w.set_idmaen(true));
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}
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regs.dctrl().modify(|w| {
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@ -1043,16 +1046,13 @@ impl SdmmcInner {
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let regs = self.0;
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unsafe {
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cfg_if::cfg_if! {
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if #[cfg(sdmmc_v1)] {
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regs.dctrl().modify(|w| {
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w.set_dmaen(false);
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w.set_dten(false);
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});
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} else if #[cfg(sdmmc_v2)] {
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regs.idmactrlr().modify(|w| w.set_idmaen(false));
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}
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}
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#[cfg(sdmmc_v1)]
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regs.dctrl().modify(|w| {
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w.set_dmaen(false);
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w.set_dten(false);
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});
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#[cfg(sdmmc_v2)]
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regs.idmactrlr().modify(|w| w.set_idmaen(false));
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}
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}
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