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stm32/rcc: fix build on l0 chips without CRS

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This commit is contained in:
Dario Nieuwenhuis 2022-02-24 05:57:17 +01:00
parent cb8a7d00d5
commit e8ca5f9b04
1 changed files with 6 additions and 1 deletions
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7
embassy-stm32/src/rcc/l0.rs
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@ -1,5 +1,7 @@
use crate::pac::rcc::vals::{Hpre, Msirange, Plldiv, Pllmul, Pllsrc, Ppre, Sw};
use crate::pac::{CRS, RCC, SYSCFG};
use crate::pac::RCC;
#[cfg(crs)]
use crate::pac::{CRS, SYSCFG};
use crate::rcc::{set_freqs, Clocks};
use crate::time::Hertz;
use crate::time::U32Ext;
@ -180,6 +182,7 @@ pub struct Config {
pub ahb_pre: AHBPrescaler,
pub apb1_pre: APBPrescaler,
pub apb2_pre: APBPrescaler,
#[cfg(crs)]
pub enable_hsi48: bool,
}
@ -191,6 +194,7 @@ impl Default for Config {
ahb_pre: AHBPrescaler::NotDivided,
apb1_pre: APBPrescaler::NotDivided,
apb2_pre: APBPrescaler::NotDivided,
#[cfg(crs)]
enable_hsi48: false,
}
}
@ -312,6 +316,7 @@ pub(crate) unsafe fn init(config: Config) {
}
};
#[cfg(crs)]
if config.enable_hsi48 {
// Reset SYSCFG peripheral
RCC.apb2rstr().modify(|w| w.set_syscfgrst(true));