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stm32f2: Avoid resetting rtc backup domain

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Also ensure the pwr is enabled before trying to initialize. For the F2
series this is in a seperate clock control register.
This commit is contained in:
Scott Mabin 2023-07-30 21:22:48 +01:00
parent f3237d7a2c
commit e8d3e86591
1 changed files with 6 additions and 2 deletions
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8
embassy-stm32/src/rtc/v2.rs
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@ -39,9 +39,8 @@ impl<'d, T: Instance> super::Rtc<'d, T> {
let rtcsel = reg.rtcsel().to_bits(); let rtcsel = reg.rtcsel().to_bits();
if !reg.rtcen() || rtcsel != clock_config { if !reg.rtcen() || rtcsel != clock_config {
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))] #[cfg(not(any(rtc_v2l0, rtc_v2l1, rtc_v2f2)))]
crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true)); crate::pac::RCC.bdcr().modify(|w| w.set_bdrst(true));
#[cfg(not(any(rtc_v2l0, rtc_v2l1)))] #[cfg(not(any(rtc_v2l0, rtc_v2l1)))]
let cr = crate::pac::RCC.bdcr(); let cr = crate::pac::RCC.bdcr();
#[cfg(any(rtc_v2l0, rtc_v2l1))] #[cfg(any(rtc_v2l0, rtc_v2l1))]
@ -201,6 +200,11 @@ impl sealed::Instance for crate::peripherals::RTC {
// read to allow the pwr clock to enable // read to allow the pwr clock to enable
crate::pac::PWR.cr1().read(); crate::pac::PWR.cr1().read();
} }
#[cfg(any(rtc_v2f2))]
{
crate::pac::RCC.apb1enr().modify(|w| w.set_pwren(true));
crate::pac::PWR.cr().read();
}
} }
fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> { fn read_backup_register(rtc: &Rtc, register: usize) -> Option<u32> {