enable clock first
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@@ -64,7 +64,7 @@ impl<'d, T: Instance> Adc<'d, T> {
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into_ref!(adc);
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T::reset_and_enable();
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T::enable_and_reset();
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// Enable the adc regulator
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T::regs().cr().modify(|w| w.set_advregen(vals::Advregen::INTERMEDIATE));
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